60results about How to "Increase gate width" patented technology

A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.

An organic thin film transistor comprising: a substrate; a source electrode and a drain electrode defining a channel; a layer of insulating material disposed over the source and drain electrodes; a layer of organic semi-conductive material extending across the channel; a layer of dielectric material; and a gate electrode disposed over the layer of dielectric material.

A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Provided is a semiconductor device having a structure in which: a well region of a high resistance p-type semiconductor is disposed in a given depth from a surface of an n-type or p-type semiconductor substrate; a plurality of trenches extend from the surface of the well region to a certain depth; a gate insulating film is formed on a surface of a convex/concave portion on which the trenches are formed; a gate electrode is embedded into the trenches. The semiconductor device includes: a gate electrode film that is disposed on a substrate surface in contact with the gate electrode embedded into the trenches in the convexo-concave portion region except for a portion in the vicinity of both ends of the trenches; and a source region and a drain region that are two low resistance n-type semiconductor layers which are disposed shallower than the depth of the well region in the well region except for a lower portion of the gate electrode film.

In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first polygonal shapes and the second polygonal shapes, respectively. With this configuration, the forward transfer admittance gm can be increased as compared with a structure in which gate regions are disposed in a stripe pattern. Furthermore, compared with a case in which a gate region is disposed in a grid pattern, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacitance Ciss can be minimized while a predetermined withstand voltage is maintained.

A new front-end module is disclosed. In an embodiment the front-end module is configured to operate carrier aggregation modes using a cascade of switches and an intelligent set of bands. The module can be assembled by sub-modules.

A semiconductor device includes a gate on a semiconductor substrate. One side wall of the gate may include at least one protrusion and an opposite side wall of the gate may include at least one depression. A contact is formed through an insulating layer disposed over the gate. The contact at least partially overlaps at least one of the protrusions in the gate. A metal layer is disposed on the insulating layer. The metal layer includes a first structure shifted to a first side of the gate. The first structure at least partially overlaps the contact such that the contact electrically couples the first structure to the gate through the insulating layer.

A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.

A wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. The receiver includes an AGC controller which controls the timing at which the programmable gain amplifiers make gain change, using a terminal counter and a sequencer. The receiver prevents gain change noise signals during the reception of control signals and other signals that are susceptible to noise. By the timing control feature, the programmable gain amplifiers make gain change while reducing noise impact.

The invention discloses an interdigital structure capable of regulating the channel current of vertical gate SOI CMOS devices, which comprises a plurality of vertical gate SOI CMOS devices which are distributed in parallel, wherein PMOS regions of the adjacent vertical gate SOI CMOS devices are adjacent, and NMOS regions are also adjacent; source regions of all of the vertical gate SOI CMOS devices are positioned on the same side, and drain regions are positioned on the other side; and gate electrodes of all of the vertical gate SOI CMOS devices are led out of the side surface to form interdigital gate electrodes. The adjacent PMOS regions share one body electrode; the adjacent NMOS regions share one body electrode; and all of the body electrodes are connected in parallel to form an interdigital body electrode. All source electrodes led out from the source regions are connected in parallel to form an interdigital source electrode; and all drain electrodes led out from the drain regions are connected in parallel to form an interdigital drain electrode. In the invention, the gate electrodes of the plurality of the CMOS devices are connected in parallel by an interdigital topological structure, which is equivalent to improving the equivalent gate width of the vertical gate SOI CMOS devices so as to fulfill the aim of regulating the channel current of the vertical gate SOI CMOS devices.

A low voltage, switch mode PHEMT power amplifier with a 0.1 μm gate length and a low loss, lumped element, output matching circuit is disclosed that provides high performance over a frequency range of 1.4 GHz-2.5 GHz. The amplifier makes use of monolithic circuit technology for the first stage and output transistor, and uses a printed circuit board with surface mount components for the output matching network. The power output of the power amplifier is stable over a range of 60 degrees centigrade, has high power efficiencies of 44-53% with greater than 2 watts output power over the frequency range of 1.4 GHz and 2.5 GHz. In addition, through drain voltage control, the output power can be varied over a wide range between about 0.8 to 2.5 watts while still maintaining a high efficiency in the range of 50±3%.

A liquid crystal display device having thin film transistors which can alleviate the required alignment accuracy of a semiconductor film while suppressing the generation of an optical leak current is provided. The liquid crystal display device includes: a transparent substrate; gate electrodes which are stacked above the transparent substrate; source electrodes and drain electrodes which are stacked above the gate electrodes; and semiconductor films each of which is stacked above the gate electrode and controls an electric current between the source electrode and the drain electrode based on an electric field generated by the gate electrode, wherein the semiconductor film is formed into a planar shape, and includes a first region which overlaps with the gate electrode in plane and a second region which does not overlap with the gate electrode in plane, and the source electrode and the drain electrode are not connected to the semiconductor film in the second region, and are connected to the semiconductor film in the first region.

The invention discloses a DRAM and a forming method thereof. The method comprises the following steps: after the active region and the isolation layer are etched to form a word line trench, continuously etching the isolation layer along the side wall of the word line trench in the isolation layer, so that the width of the word line trench in the isolation layer is increased, and the width of the part of the word line trench in the isolation layer is greater than that of the part of the word line trench in the active region; and forming a word line structure in the word line trench, wherein thewidth of the part of word line structure in the isolation layer is greater than the width of the part of word line structure in the active region. The formed word line structure is wavy, so that on one hand, the resistance of the word line structure is reduced; and on the other hand, a channel is formed at the boundary of the active region, that is, the width of the conductive channel of a deviceis increased, and the conduction current of the transistor of the DRAM is increased, so that the reading speed of memory is increased, and the integration level of the transistor of the DRAM is increased.

A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a circle or polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode.