3D semiconductor device and forming method thereof

Abstract

The invention provides a 3D semiconductor device and a forming method thereof, and is applied to the technical field of semiconductors. According to the forming method of the 3D semiconductor device provided by the invention, a grid electrode is shared by two adjacent MOS devices, the grid electrode and the drain electrode / source electrodes of the MOS devices are arranged on the surface of the semiconductor substrate, and the grid electrode and the drain electrode / source electrodes are horizontally connected, so that the width of the grid electrode of the MOS devices can be increased in the vertical direction, the 3D semiconductor device can be formed, and the channel length of the MOS device is increased, and the wafer area can be saved under the condition of reducing the short channel effect of the MOS device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a 3D semiconductor device and a forming method thereof. Background technique [0002] The scaling of features in integrated circuits has been the driving force behind the continued growth of the semiconductor industry over the past few decades. Scaling to smaller and smaller features enables increased densities of functional units on the limited chip area of ​​semiconductor chips. For example, shrinking transistor size allows combining increased numbers of memory or logic devices on a chip, resulting in products with increased capacity. However, the drive to greater and greater capacity is not without its problems. The need to optimize the performance of each device is becoming more and more important. [0003] At present, in the manufacture of integrated circuit devices, in order to pursue high performance of devices and save the chip area occupied by each device, the ...

AI Technical Summary

Problems solved by technology

However, when the size of the MOS device is reduced to a certain extent, the short channel effect will be caused

The short channel effect will lead to a decrease in the control ability of the gate of the MOS device, which will cause a shift in the threshold voltage and a drain-induced barrier lowering effect, resulting in an increase in the static power consumption of the MOS device

At the same time, the reduced device size will lead to an increase in the electric field inside the device, which will increase the generation of hot carriers and reduce the reliability of the device.

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