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Chip package structure and packaging method thereof

A chip packaging structure and chip packaging technology, applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc.

Active Publication Date: 2011-08-31
SILERGY SEMICON TECH (HANGZHOU) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to overcome the deficiencies in the prior art, and propose a new chip packaging structure and packaging method, which according to the type of chip contact pad Different connection methods are used to solve the problems of large chip loss, difficult heat dissipation, too many bonding wires and the limitation of packaged chip function expansion

Method used

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  • Chip package structure and packaging method thereof
  • Chip package structure and packaging method thereof
  • Chip package structure and packaging method thereof

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Embodiment Construction

[0042] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any alternatives, modifications, equivalent methods and schemes made on the spirit and scope of the present invention. In order to provide the public with a thorough understanding of the present invention, specific details are set forth in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without the description of these details.

[0043] figure 2 What is shown is a schematic diagram of a chip package structure according to an embodiment of the present invention. The chip package structure of this embodiment includes a chip 201 , a lead frame 203 , a first bonding wire 206 - 1 and a second bonding wire 206 - 2 . The chip 201 has a first contact pad 202-1 and a second cont...

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Abstract

The invention relates to a chip package structure and a packaging method thereof. The structure comprises at least one chip, wherein each chip is provided with a plurality of first contact pads and second contact pads, a lead frame, a group of first bonding wires and a group of second bonding wires, wherein the lead frame comprises a plurality of pins for external connection; the chip is arrangedon the lead frame; the group of the first bonding wires are used for directly and electrically connecting the first contact pads to the lead frame; and the group of the second bonding wires are used for electrically connecting the second contact pads to the plurality of pins of the lead frame. The structure and the method can conveniently realize the chip with low consumption and easy heat dissipation, reduce packaging size of the chip, and contribute to the function expansion of the chip.

Description

technical field [0001] The invention relates to a chip packaging structure and a packaging method thereof, belonging to semiconductor elements and a manufacturing method thereof. Background technique [0002] In the semiconductor industry, the production of integrated circuits can be divided into three stages: integrated circuit design, integrated circuit manufacturing and integrated circuit packaging. In the manufacture of integrated circuits, chips are completed by the steps of wafer manufacturing, forming integrated circuits, and cutting wafers. After the integrated circuit inside the wafer is completed, a plurality of bonding pads are arranged on the wafer, so that chips formed by dicing the wafer can be electrically connected to a carrier externally through these bonding pads. The carrier is, for example, a lead frame or a package substrate. The chip can be connected to the carrier by wire bonding or flip-chip bonding, so that the pads of the chip can be electrically ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/485H01L21/60
CPCH01L2924/01023H01L2924/01082H01L2924/00014H01L2224/49113H01L24/06H01L2924/01029H01L23/4952H01L2924/01028H01L2924/19041H01L2924/014H01L2224/49171H01L2924/30107H01L2224/85447H01L24/49H01L2224/4917H01L24/48H01L2924/01079H01L2224/48247H01L2224/45099H01L2924/14H01L2924/01005H01L2924/01033H01L2924/01006H01L2924/01014H01L2224/48257H01L2924/01075H01L2224/49175H01L2224/05553H01L2224/05554H01L2924/10161Y10T29/5313H01L2224/05599H01L2924/00
Inventor 谭小春陈伟
Owner SILERGY SEMICON TECH (HANGZHOU) CO LTD
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