Chip package structure and packaging method thereof

Abstract

The invention relates to a chip package structure and a packaging method thereof. The structure comprises at least one chip, wherein each chip is provided with a plurality of first contact pads and second contact pads, a lead frame, a group of first bonding wires and a group of second bonding wires, wherein the lead frame comprises a plurality of pins for external connection; the chip is arrangedon the lead frame; the group of the first bonding wires are used for directly and electrically connecting the first contact pads to the lead frame; and the group of the second bonding wires are used for electrically connecting the second contact pads to the plurality of pins of the lead frame. The structure and the method can conveniently realize the chip with low consumption and easy heat dissipation, reduce packaging size of the chip, and contribute to the function expansion of the chip.

Description

technical field

[0001] The invention relates to a chip packaging structure and a packaging method thereof, belonging to semiconductor elements and a manufacturing method thereof. Background technique

[0002] In the semiconductor industry, the production of integrated circuits can be divided into three stages: integrated circuit design, integrated circuit manufacturing and integrated circuit packaging. In the manufacture of integrated circuits, chips are completed by the steps of wafer manufacturing, forming integrated circuits, and cutting wafers. After the integrated circuit inside the wafer is completed, a plurality of bonding pads are arranged on the wafer, so that chips formed by dicing the wafer can be electrically connected to a carrier externally through these bonding pads. The carrier is, for example, a lead frame or a package substrate. The chip can be connected to the carrier by wire bonding or flip-chip bonding, so that the pads of the chip can be electrically ...

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