Digital signal processor with reconfigurable low power consumption data interleaving network

Abstract

The invention discloses a digital signal processor with a reconfigurable low power consumption data interleaving network, which comprises an N-channel parallel vector operation unit, an N-channel parallel vector register file, an N-channel parallel vector memory and an N-channel reconfigurable parallel data interleaving network, wherein the N-channel reconfigurable parallel data interleaving network is used for connecting the N-channel parallel vector operation unit, the N-channel parallel vector register file and the N-channel parallel vector memory and managing data transmission therein. The utilization of the digital signal processor can lead data to realize the continuous uninterrupted parallel transmission and directly input to an operand from an operation result bypass of the N-channel parallel vector operation unit when necessary without passing through the N-channel parallel vector register file and/or the N-channel parallel vector memory through the N-channel reconfigurable parallel data interleaving network, thereby overcoming the technical limitations of the traditional data transmission management, improving the data transmission efficiency, reducing the power consumption and meeting the needs of data interweaving in different widths.

Description

technical field [0001] The invention relates to the technical field of digital signal processors and microprocessors, in particular to a digital signal processor with a reconfigurable low-power data interleaving network. Background technique [0002] With the rapid development of computer and information science, digital signal processing (DSP) technology emerges at the historic moment and develops rapidly. In today's digital age, all applications including communication and consumer electronics, especially real-time and portable electronic products, require high-performance, low-power digital signal processors for various digital signal processing. [0003] The traditional scalar digital signal processor cannot take full advantage of the large amount of parallelism in the digital signal processing algorithm. With the rapid development of integrated circuit technology, more and more transistors can be integrated in the same chip, which allows us to use vector and Multi-core...

AI Technical Summary

Problems solved by technology

[0005] 1), low efficiency

Traditional data transmission is based on a single address transmission, which is not suitable for discontinuous data transmission. The efficiency of interleaved data transmission in the algorithm is low, and the degree of parallelism is low. It is impossible to provide operands and return results to the operation unit in time.

[0006] 2), high power consumption

In the traditional way, data needs to be frequently transmitted between the computing unit and the memory, which consumes a lot of energy, which leads to an increase in power consumption, which is not conducive to the stability of the chip.

A large amount of power consumption not only limits the application of the product in the portable embedded field, but also causes a series of problems such as increased maintenance costs and decreased system stability even in large-scale supercomputing platforms

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