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Method and device for enhancing persistence of EEPROM

A technology of persistence and electric field strength, which is applied in the field of enhancing EEPROM persistence, can solve the problems of insufficient EEPROM persistence, achieve the effect of shortening writing and erasing time and enhancing durability

Active Publication Date: 2010-10-13
FREMONT MICRO DEVICES SHENZHEN LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method that can control the electric field strength on the gate oxide layer within a reasonable range, reduce its peak value, and further enhance the durability of EEPROM. persistent method

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  • Method and device for enhancing persistence of EEPROM
  • Method and device for enhancing persistence of EEPROM
  • Method and device for enhancing persistence of EEPROM

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Embodiment Construction

[0032] The key of the present invention is that for the EEPROM adopting the floating gate tunnel oxide structure, a controllable high voltage signal is used to control the electric field intensity of the gate oxide layer between 10MV / cm-15MV / cm during erasing or writing. For the high-voltage controllable signal, its rising speed and specific size can be determined according to actual conditions.

[0033] In one embodiment of the present invention, when the electric field strength of the gate oxide layer is less than 10MV / cm, the controllable high voltage signal rises at a first speed; when the electric field strength of the gate oxide layer is equal to 10MV / cm, the The controllable high-voltage signal rises at a second speed and controls the electric field strength of the gate oxide layer between 10MV / cm and 15MV / cm, wherein the second speed is lower than the first speed. In an embodiment of the present invention, The electric field strength of the gate oxide layer may be samp...

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Abstract

The invention relates to a method and a device for enhancing persistence of EEPROM. The method comprises the step of: controlling the electric field strength of a gate oxide layer to be within the range from 10 to 15MV / cm by using a controllable high-voltage signal during the erasing or writing for an EEPROM with a floating gate tunnel oxide structure. The device comprises a clock generating drive circuit and a charge pump, wherein the clock generating drive circuit is used for generating a clock drive signal; the charge pump is used for generating a controllable high voltage signal according to the clock drive signal; and the controllable high voltage signal is used for controlling the electric field strength of the gate oxide layer to be within the range from 10 to 15MV / cm during the erasing or writing of the EEPROM with the floating gate tunnel oxide structure. By controlling the electric field strength on the gate oxide layer to be within a reasonable range, the device for enhancing the persistence of the EEPROM reduces the peak value so as to effectively enhance the persistence; and the writing and erasing time can also be shortened by using different controllable high voltage signal rising velocities.

Description

technical field [0001] The invention relates to the field of memory circuit design, more specifically, to a method and device for enhancing EEPROM persistence. Background technique [0002] Electrically Erasable Programmable Read-Only Memory (EEPROM) usually adopts a floating gate tunneling oxide (FLOTOX, floating gate tunneling oxide) structure, such as figure 1 shown. The FLOTOX structure uses the electron flow generated by the F-N (Fowler-Nordheim) tunnel effect to erase and write data on the floating gate. Under the action of the voltage difference, the barrier width between the silicon and the oxide layer becomes thinner, allowing electrons to pass through the barrier layer and cross between the conduction band of the silicon and the conduction band of the oxide layer, realizing electron injection and erasing of the floating gate . The processes of electron injection and erasure are as follows figure 2 a and figure 2 As shown in b. Among them, the relationship b...

Claims

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Application Information

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IPC IPC(8): G11C19/10G11C16/30G11C16/06
Inventor 邓锦辉刘阳胡小波施爱群
Owner FREMONT MICRO DEVICES SHENZHEN LTD
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