Board-level circuit programmable multi-FPGA (Field Programmable Gate Array) verification system adopting high-speed electronic switch array

Abstract

The invention relates to a board-level circuit programmable multi-FPGA (Field Programmable Gate Array) verification system adopting a high-speed electronic switch array. For hardware, the three-dimensional high-speed electronic switch array is adopted to realize programmable connection among multiple FPGA chips positioned on a same circuit board, the programmable connection from each FPGA to a stacked expansion socket for achieving the stacked expansion of a system, the programmable connection from each FPGA to an external expansion socket and the programmable connection of the FPGA chips positioned between an upper layer and a lower layer of the stacked expansion system; a multi-level clock cascading method is adopted to realize the synchronization of clock signals among the FPGA; and an annular bus is adopted to realize the fast communication of the multi-FPGA and a mainframe. For software, a realization method of a self-checking software tool of the system, a realization method of a switch array user programming interface and an automatic computation software tool of the system and an annular bus based realization method of software and hardware cooperated simulation acceleration are included. The invention can be used for the real-time prototype verification of ASIC (Application Specific Integrated Circuit) chips with a scale from 6, 000, 000 gates to 30, 000, 000 gates and the hardware acceleration simulation.

Description

technical field [0001] The present invention relates to a multi-FPGA prototype verification and software-hardware co-simulation acceleration system design that needs to be adopted in large-scale ASIC design. The scalable multi-FPGA solution, as well as the high-speed electronic switch array and supporting control software used at the board level make the system in Board-level programmable and scalable, suitable for real-time prototype verification of large-scale ASIC chips with 6 million to 30 million gates and software and hardware coordinated acceleration simulation. Through the high-speed ring bus and supporting software implemented on this verification system, all control and programming operations on the system can be realized; and through this high-speed bus and PLI software simulation interface, the software-hardware co-acceleration emulator function of the ASIC chip can be realized, and its performance can reach 10 to 100 times the speed of the software emulator. Bac...

AI Technical Summary

Problems solved by technology

[0005] At present, a general consensus has been reached: the life cycle of a large-scale chip from design to mass production is getting shorter and shorter, and the method of serial design, test program development, and chip prototype verification is no longer applicable.

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