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Preparation method for integrated circuit containing DMOS transistor

A technology of integrated circuits and transistors, which is applied in the field of integrated circuit preparation, can solve problems that affect device efficiency and increase the overall size, and achieve the effects of ensuring efficiency, reducing size, and reducing requirements

Active Publication Date: 2012-04-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This causes the overall size of the device to become larger, which affects the efficiency of the device.

Method used

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  • Preparation method for integrated circuit containing DMOS transistor
  • Preparation method for integrated circuit containing DMOS transistor
  • Preparation method for integrated circuit containing DMOS transistor

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Experimental program
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Embodiment Construction

[0024] The preparation method of the integrated circuit including the DMOS transistor of the present invention, after the polysilicon gate is formed, the specific process can be found in Figure 7 , including the following steps:

[0025] 1) Deposit a thin film used as a side wall on the substrate forming the polysilicon gate (see Figure 8 ), the film is conventionally used as a sidewall material, which can be a silicon nitride film or a silicon oxide film;

[0026] 2) Using a photolithography process to make the photoresist cover the thin film used as a side wall that is to be formed as a hard mask above the high-voltage drift injection region in the DMOS transistor, including a part of the polysilicon gate and the high-voltage drift injection region In principle, the part where the drain region is planned to be formed is exposed;

[0027] 3) Etching (generally dry etching) exposed film used as a side wall, after etching, a side wall is formed on one side of the polysilico...

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Abstract

The invention discloses a preparation method for an integrated circuit containing a DMOS transistor. After a polycrystalline silicon grid is formed, the method comprises the following steps of: 1) depositing a film used as a side wall; 2) covering a photoresist on the film which is positioned on a high-pressure drifting and injecting region in the DMOS transistor, provided with a preformed rigid mask and is used as the side wall by using a photoetching process; 3) etching the film used as the side wall to form the side wall on one side of the polycrystalline silicon grid and form the rigid mask on the other side of the polycrystalline silicon grid; 4) extracting the formed body out of the injecting region; 5) forming a source / drain region; and 6) preparing self-aligned metal silicide. Thepreparation method can reduce the size of devices so as to ensure the efficiency of the devices.

Description

technical field [0001] The invention relates to a method for preparing an integrated circuit including a DMOS transistor. Background technique [0002] In the manufacture of power and high voltage integrated circuits, DMOS (Lateral Metal Oxide Semiconductor) devices are often used to provide large output current and high output voltage. In the DMOS structure, the distance from the polysilicon gate to the drain terminal (source-drain injection region or silicon metallization region) will directly affect the breakdown voltage and on-resistance of the device. [0003] In the existing process such as Figure 1-Figure 6 Shown as: [0004] (1) After the polysilicon gate is formed, a film used as a sidewall is deposited on the substrate surface (see figure 1 ); [0005] (2) Etching the sidewall film to form sidewalls on both sides of the polysilicon gate (see figure 2 ); [0006] (3) The body implantation region, the source region and the drain region are formed step by step...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L21/336H01L21/027
Inventor 陈华伦陈瑜熊涛罗啸陈雄斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP