Image processing device for image data
An image processing device and image data technology, applied in image data processing, image data processing, instruments, etc., can solve problems such as limited bandwidth, non-real-time performance, and unsatisfactory high frame frequency, so as to reduce cycle time, increase bandwidth, and upgrade simple effect
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- Publication Date
- 2010-12-15
- Estimated Expiration
- Not applicable · inactive patent
Smart Images
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Abstract
Description
technical field
[0001] The present invention relates to image processing and image acquisition, the field of image communication, in particular to the high-speed real-time acquisition of image data of Camera link interface type based on programmable logic gate array FPGA and digital signal processor DSP, based on external memory interface EMIF and gigabit High-speed real-time transmission and display device of network transceiver module Ethernet MAC. Background technique
[0002] In traditional image processing, image acquisition is often the first link. The general acquisition device is an image acquisition card used in conjunction with a personal computer. The acquisition card is inserted into the PCI slot of the personal computer, and the collected image data Store it on the hard disk of the personal computer, and then analyze and process the collected images, including image enhancement, image compression, image communication and other processing methods. Such an acquis...
Examples
Embodiment Construction
[0032] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0033] The method described in the present invention is realized by the external memory interface (EMIF) between the programmable logic gate array 2 (FPGA) and the digital signal processor 3 (DSP) and two general-purpose input and output pins (GPIO) signals, will The programmable logic gate array 2 is configured as a master device (Master), and the digital signal processor 3 is configured as a slave device (Slave), forming a master-slave structure, so that the programmable logic gate array 2 can generate a write request, Write data to the digital signal processor 3 . The external memory interface adopts a synchronous mode, which can simplify the circuit and reduce the resources occupied by the programmable logic gate arra...