Quick access nonvolatile memory cell with double-transistor structure

Abstract

The invention discloses a quick access nonvolatile memory cell with a double-transistor structure, which is characterized in that a left and a right N+ source leakage doped regions are formed on a P well; an N buried layer is arranged between the two N+ source leakage doped regions; ONO multi-medium structure gate oxide is arranged on the N buried layer near to the left N+ source leakage doped region, and polycrystalline silicon is arranged on the ONO multi-medium structure gate oxide to form an SONOS (Silicon Oxide Nitride Oxide Semiconductor) transistor gate; an HTO oxide layer is arranged on the N buried layer near to the right N+ source leakage doped region, and the polycrystalline silicon is arranged on the HTO oxide layer; the HTO oxide layer and the polycrystalline silicon on the HTO oxide layer extend towards one side and cover on the polycrystalline silicon on the ONO multi-medium structure gate oxide to form a selectron gate; and a silicon nitride isolated layer is arranged between the two layers of the polycrystalline silicon to form a composite gate structure. The memory cell has the advantage of small area.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, in particular to a fast-access non-volatile memory unit with a two-transistor structure. Background technique [0002] The cross-sectional schematic diagram of the current mainstream 2T FLASH NVM (two-transistor structure fast access non-volatile memory) memory cell is shown in figure 1 As shown, it consists of a SONOS (silicon-oxide-nitride-oxide-silicon) transistor and a FLASH NPASS FET (selection tube), the SONOS (silicon-oxide-nitride-oxide-silicon) transistor , is to form two N+ source and drain doped regions on the P well, between the two N+ source and drain doped regions is an N-type depletion channel, and above the N-type depletion channel is an ONO (oxide-nitrogen compound-oxide) multi-dielectric structure gate oxide, the ONO multi-dielectric structure gate oxide is a polysilicon gate, and the FLASH NPASS FET (selection transistor) is to form two N+ source and drain ...

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Problems solved by technology

figure 1 The current mainstream 2T FLASH NVM storage unit shown has three N+ source-drain doped regions in total, and the area of ​​the memory unit is relatively large, especially in products with large storage capacity, which will result in a chip area used for data storage. Large, increases manufacturing cost

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