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Manufacture method of semiconductor device and flash memory device

A manufacturing method and technology of flash memory devices, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as reducing product quality rate

Active Publication Date: 2012-07-25
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The purpose of the embodiments of the present invention is to provide a method for manufacturing semiconductor devices and flash memory devices, so as to solve the problems that the existing semiconductor devices can only use dry etching technology to reduce the product quality rate in the manufacturing process.

Method used

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  • Manufacture method of semiconductor device and flash memory device
  • Manufacture method of semiconductor device and flash memory device
  • Manufacture method of semiconductor device and flash memory device

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Embodiment Construction

[0026] In order to make the above-mentioned purpose, characteristics and advantages of the present invention more obvious and understandable, a preferred embodiment is listed below, and in conjunction with the accompanying drawings, the detailed description is as follows:

[0027] The following are examples describing the present invention, which disclose the main technical features of the present invention, but are not intended to limit the present invention.

[0028] Please refer to Figure 2A , provide a substrate 202, including an array region 204 and a peripheral region 206, the material of the substrate 202 is silicon, for example. A pad layer 210 such as silicon oxide is formed on the substrate 202 , and a hard mask layer 212 such as silicon nitride is formed on the pad layer 210 . Next, pattern the hard mask layer 212 and pad layer 210 , and use the patterned hard mask layer 212 as a mask to etch the substrate 202 to form a plurality of trenches 208 . Please refer to...

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PUM

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Abstract

The embodiment of the invention provides a manufacture method of a semiconductor device and a flash memory device. The manufacture method of the semiconductor device comprises the following steps: providing a substrate; forming a graphical hard mask layer on the substrate; etching the substrate by the hard mask layer, and forming a plurality of grooves in the substrate; forming a rotary coating dielectric layer on the substrate, and filling in the grooves; carrying out a first grinding process; forming patterning photoresist; carrying out a first back etching process, and etching the rotary coating dielectric layer which is not covered by the patterning photoresist and is formed on the peripheral area; removing the patterning photoresist; carrying out a second back etching process, and back etching the rotary coating dielectric layers in an array region and a groove in the peripheral area; forming a high-density plasma dielectric layer on the rotary coating dielectric layer in the groove; and carrying out a second grinding process, and forming a plurality of shallow groove isolation structures. In the embodiment of the invention, a wet etching technology is adopted to realize the back etching process of the semiconductor device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device and a flash memory device. Background technique [0002] With the current trend of increasing the density of devices, the distance between the floating gate and the floating gate of the stacked-gate type flash memory is getting closer and closer, so that the floating gate and the isolation dielectric Formation of self-aligned floating gates between layers has become a necessary condition for manufacturing process scaling. With the shrinking of the manufacturing process, the most common method for forming self-aligned floating gates is to form a shallow trench isolation process between the isolation dielectric layer and the active region, and then between the isolation dielectric layer and the isolation dielectric layer. A tunnel oxide layer is grown on the active area, and then polysilicon used as a floating gate is deposit...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/311H01L21/8247
Inventor 倪志荣余志杰
Owner WINBOND ELECTRONICS CORP
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