Method for manufacturing semiconductor device

Abstract

The invention discloses a method for manufacturing a semiconductor device. The method comprises the following the steps of: providing a substrate; forming a gate electrode oxide layer and a gate electrode on the substrate; forming a clearance wall insulation layer on the gate electrode oxide layer and the side wall of the gate electrode, and meanwhile, forming a first insulation layer at the backside of the substrate; forming clearance wall on the side wall of the clearance wall insulation layer, and meanwhile, forming a second insulation layer at the back side of the first insulation layer;forming a source electrode and a drain electrode on the substrate; forming an etching stopping layers on the clearance wall; forming a high-stress induction layer on the etching stopping layer; and carrying out N20 treatment on the high-stress induction layer. The method disclosed in the invention can effectively prevent a photoresist poisoning problem caused by the formation of a SiN layer in the stress memory technology so as to reduce the production cost of the semiconductor device and improve the rate of good products.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a manufacturing process for preventing photoresist poisoning in a stress memory process. Background technique [0002] The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Considering the excellent characteristics of operation speed, power consumption and cost efficiency, CMOS technology is currently one of the most promising methods for manufacturing complex circuits. In the fabrication of complex integrated circuits using CMOS technology, millions of transistors (eg, N-channel transistors and P-channel transistors) are formed on a substrate comprising crystalline semiconductor layers. Regardless of whether N-channel or P-channel transistors are being studied, MOS transistors contain a so-called PN junction formed by the interface of a highly doped drain / source re...

AI Technical Summary

Problems solved by technology

Resist pinching can result when using negative-tone photoresists due to the formation of non-uniform sidewalls of the photoresist profile on the underlying substrate after photolithographic exposure and development. Resist pedestal or resist pinching issues will result in incomplete transfer of the resist pattern to underlying layers

like figure 2 As shown, the original required critical dimension has shifted abnormally, shrinking from 180nm to 140nm, which will cause serious process deviation, which will affect the performance of semiconductor devices manufactured later, which is not expected.

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