Method for preparing semiconductor device

Abstract

The invention discloses a method for preparing a semiconductor device, which comprises the following steps of: providing a substrate, wherein a shallow trench isolation region and a well region are formed on the substrate; forming a gate oxide layer on the well region and the shallow trench isolation region; forming a grid on the gate oxide layer; performing lightly doped ion implantation to form a lightly dope drain region on the substrate by taking the grid as a mask; forming an oxide layer on the grid and the gate oxide layer and etching the oxide layer to form a side wall oxide layer on the side wall of the grid; performing ion implantation with the grid and the side wall oxide layer as masks to form a source electrode and a drain electrode on the substrate; and performing fast thermal annealing process and raising the annealing temperature at the speed of 50-200 DEG per second till the annealing temperature reaches 900-1100 DEG C. The change degree of static current Idsat of the transistors with the same size can be reduced according to the control method of peak annealing temperature so as to improve the yield of the device.

Description

technical field [0001] The present invention relates to semiconductor manufacturing process, and in particular to a method for controlling the temperature of rapid thermal annealing. Background technique [0002] In the semiconductor process, when forming the source and drain regions of a semiconductor device with silicon as the substrate material, an ion implantation process is usually used to implant dopants or impurity atoms on the side of the wafer with elements. However, the ion implantation process will damage the crystal lattice structure of the wafer surface, and part of the implanted impurity atoms will remain in the interstitial positions of the crystal lattice without generating electricity. In order to move all the impurity atoms to replacement positions in the crystal lattice so that these atoms become electrically charged, and to repair the lattice structure damaged during the ion implantation process, the wafer is usually subjected to an annealing process to h...

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Problems solved by technology

However, using the above heating conditions, the transistor I dsat The sigma value is larger, indicating that the transistor I of the same batch size dsat The variation is too large, which will cause inconsistent performance of the same batch of devices, resulting in a decrease in the yield of the device

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