Unlock instant, AI-driven research and patent intelligence for your innovation.

Forming method of ultra shallow junction structure and forming method of PMOS (P-Channel Metal Oxide Semiconductor) transistor

A transistor, ultra-shallow technology, applied in the direction of transistor, semiconductor device, semiconductor/solid-state device manufacturing, etc.

Inactive Publication Date: 2011-06-01
CSMC TECH FAB1 +1
View PDF1 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] However, the above process still needs to be further optimized to further increase the threshold voltage of the transistor

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Forming method of ultra shallow junction structure and forming method of PMOS (P-Channel Metal Oxide Semiconductor) transistor
  • Forming method of ultra shallow junction structure and forming method of PMOS (P-Channel Metal Oxide Semiconductor) transistor
  • Forming method of ultra shallow junction structure and forming method of PMOS (P-Channel Metal Oxide Semiconductor) transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] In the method of the present invention, the implantation of boronous fluoride ions is carried out before the amorphization of the substrate, and the feature that the fluorine ions are easier to diffuse in the state of crystalline silicon is utilized, so that the fluorine ions in the crystalline silicon can more easily make the grid on the surface of the substrate The silicon-oxygen bond in the polar dielectric layer is broken, and the oxygen ions detached from the silicon-oxygen bond will oxidize the substrate silicon near the gate dielectric layer, which leads to the increase of the gate dielectric layer. Among them, the formula combined with the above body effect value is as follows:

[0046] γ = 2 ϵ 0 q N a / Cox

[0047] The increase of the gate dielectric layer will directly lead to Cox in the formula, that is, the r...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a forming method of an ultra shallow junction, which comprises the following steps of: providing a semiconductor substrate; implanting first ions in the semiconductor substrate to form a first implantation zone; implanting second ions in the first implantation zone and decrystallizing the first implantation zone; and implanting third ions in the decrystallized first implantation zone to form the ultra shallow junction structure, wherein the first ions are boron fluorate ions, the second ions are tetravalent ions, and the third ions are boron ions. The invention also provides a forming method of a PMOS (P-Channel Metal Oxide Semiconductor) transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming an ultra-shallow junction structure and a method for forming a PMOS transistor. Background technique [0002] Ion implantation technology is an impurity doping technology widely used in the formation of various semiconductor devices and integrated circuits. By controlling the current and voltage of the implanted ion beam, the content and distribution of impurities in the semiconductor substrate can be precisely adjusted. [0003] As we all know, the feature size of semiconductor devices is getting smaller and smaller with the innovation of process technology. According to the requirement of proportional reduction, while the lateral dimension of the device (ie, the line width represented by the feature size) is continuously reduced, the vertical dimension of the device (ie, the depth of the device) is also required to be proportionally reduced. Theref...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/265H01L21/336H01L21/266H01L21/82
CPCH01L29/7833H01L21/26506H01L21/26513H01L29/6659H01L21/2658
Inventor 杜建菜建瓴李佳佳王德进张克云方浩
Owner CSMC TECH FAB1