Delay lock loop and associated method

Abstract

The invention provides a delay lock loop and an associated method. The delay lock loop comprises a pulse wave generator, a delay unit, a phase detector and a control unit, wherein the pulse wave generator is used for generating a predetermined pulse wave signal and a judgment signal according to an input time pulse signal; the delay unit is used for receiving the predetermined pulse wave signal and delaying the predetermined pulse wave signal according to a numerically-controlled signal so as to generate a delayed pulse wave signal; the phase detector is used for detecting the time delay of the delayed pulse wave signal according to the judgment signal to generate a detection result signal; and the control unit is used for generating a numerically-controlled signal according to the detection result signal so as to control the delay of the predetermined pulse wave signal caused by the delay unit.

Description

technical field [0001] The present invention relates to a delay-locked loop, especially a delay-locked loop applied to a storage circuit. Background technique [0002] At present, the previous technology uses synchronous communication to achieve the high data transfer rate of DRAM. However, when DRAM technology develops to more advanced and higher-speed generations, such as the third generation of double data rate Random access memory (Double Data Rate Three Synchronous Dynamic Random Access Memory, DDR3SDRAM), originally used a phase-locked loop and an analog delay signal line to achieve synchronous communication circuits, due to technological limitations, it will not be able to achieve high transmission data rate dynamic random access memory requirements. In addition, the signal transmission between the phase-locked loop and the analog delay signal line is in the form of an analog signal, and the voltage of the analog signal is easily affected by noise, resulting in error...

AI Technical Summary

Problems solved by technology

[0002] At present, the previous technology uses synchronous communication to achieve the high data transfer rate of DRAM. However, when DRAM technology develops to more advanced and higher-speed generations, such as the third generation of double data rate Random access memory (Double Data Rate Three Synchronous Dynamic Random Access Memory, DDR3SDRAM), originally used a phase-locked loop and an analog delay signal line to achieve synchronous communication circuits, due to technological limitations, it will not be able to achieve high transmission data rate dynamic random access memory requirements

In addition, the signal transmission between the phase-locked loop and the analog delay signal line is in the form of an analog signal, and the voltage of the analog signal is easily affected by noise, resulting in errors in the data access timing or signal level of the memory. This problem is especially serious for high transfer data rate dynamic random access memory

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