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Preparation method of quasi-edge contact nano phase-change memory cell

A memory cell and nanophase technology, applied in the field of microelectronics, can solve the problems of complex process and high cost, and achieve the effects of improving device performance, low power consumption, and reducing contact area

Inactive Publication Date: 2011-06-15
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

They also have their own advantages and disadvantages, or the cost is too high, or the process is too complicated

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  • Preparation method of quasi-edge contact nano phase-change memory cell
  • Preparation method of quasi-edge contact nano phase-change memory cell
  • Preparation method of quasi-edge contact nano phase-change memory cell

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Embodiment 1

[0041] The preparation method of the memory cell structure proposed by the present invention is specifically as follows in conjunction with the accompanying drawings:

[0042] 1) Choose a low-resistance (111) silicon wafer, first use acetone to ultrasonically remove the surface organic matter, and then use concentrated H 2 SO 4 :H 2 o 2 : 1:1 heated to 100 degrees for about 5 minutes, then rinsed and dried with deionized water, then immersed the silicon wafer in a 10:1 water:HF solution for 20 seconds to remove surface oxides, and then deionized Rinse with water and shake dry, then put the wafer into NH 4 OH:H2 o 2 :H 2 O = 1: 2: 5 volume ratio of the I solution boiled for 5 minutes, then rinsed with deionized water and dried, and then put the silicon wafer into HCl: H 2 o 2 :H 2 The No. II liquid with a volume ratio of O=1:2:8 was boiled for 10 minutes, then rinsed and dried with deionized water.

[0043] 2) Deposit a dielectric layer 2 on the cleaned silicon wafer, ...

Embodiment 2

[0053] Compared with Example 1, other conditions of this embodiment remain unchanged, only the conditions of anodic oxidation in step 5 are changed, the condition is that 20wt% sulfuric acid solution is at 5°C and 18V voltage conditions, and a one-dimensional pore diameter of about 40nm can be obtained. Porous alumina. By adjusting the electrolysis voltage in the range of 10-30V, small pores of different sizes can be obtained, and the pore diameter is in the range of 10nm-100nm.

Embodiment 3

[0055] Compared with Example 1, other conditions remain unchanged in this embodiment, and only SiO in step 2 is changed. 2 The production method is that the Si-based substrate is produced by thermal oxidation method to produce SiO with a thickness of 100nm 2 medium layer.

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Abstract

The invention provides a preparation method of a quasi-edge contact nano phase-change memory cell, which specifically comprises the steps of: at first, forming an SiO2 layer on a substrate material by means of a deposition or thermal oxidization method, then depositing a layer of metal Al and a layer of SiO2 in sequence, and forming a porous medium pore of one-dimensional porous aluminum oxide in a self-organizing manner in the direction parallel to the surface of the substrate through a two-step anode oxidization process; afterwards, filling an electrode material in the porous medium pore through an electrochemical deposition method to form a horizontal columnar electrode, wherein the size of the horizontal columnar electrode is matched with that of the porous medium pore; and finally, preparing the quasi-edge contact nano phase-change memory cell by using traditional etching, a depositing phase change material and an upper electrode material.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a method for manufacturing an edge-contact phase-change memory unit for reducing RESET current Background technique [0002] Semiconductor memory represented by SRAM, DRAM and non-volatile Flash has become the most widely used basic product in the field of information electronics, and its market size accounts for nearly a quarter of the entire integrated circuit industry. With the rapid development of portable consumer electronic devices, the market share of non-volatile memory is increasing. As the current mainstream Flash non-volatile memory technology enters the 22nm process node, due to the complexity of the process, the ultra-thin oxide layer directly Various factors such as tunneling effect, leakage effect caused by stress, source-drain punch-through effect, and serious neighbor interference limit the further reduction of cell size, and the reduction of...

Claims

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Application Information

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IPC IPC(8): H01L45/00
Inventor 鄢俊兵缪向水刘昭麟程晓敏程伟明
Owner SHANDONG SINOCHIP SEMICON