Memory cell suitable for dram memory

Abstract

The present invention relates to a memory cell with a memory capacitor (110) on an active semiconductor region (104), the memory capacitor having a first capacitor- electrode layer, which, in a cross-sectional view of the memory cell, has first and second electrode-layer sections that extend on the active semiconductor region in parallel to the surface of the active semiconductor region at a vertical distance to each other and that are electrically connected by a third electrode-layer section extending vertically, that is, perpendicular to the surface of the active semiconductor region. A control transistor (112) is connected with a conductive second capacitor electrode layer that extends between the first and second electrode-layer sections and is electrically isolated from them by an isolation layer (116). Achieved advantages comprise a high manufacturing yield can, reduced fabrication cost and reduced risk of junction leakage by a small area required for the memory cell.

Description

technical field [0001] The present invention relates to memory cells and memory devices. Background technique [0002] W. Mueller et al. review the concept of scaling DRAM memory cells to 40nm in "Challenges for the DRAM Cell Scaling to 40nm", IEDM Tech. Dig., 2005, pp. 336-339. The technical issues discussed for DRAM capacitors focus on trench capacitors on the one hand and stack capacitors on the other. Scaling trench capacitors with constant cell capacitance is described as requiring increasing aspect ratios up to 120 and / or using alternative high-k dielectric materials. Similar requirements have also been reported for stacked capacitors. [0003] The disadvantage of employing trench capacitors with high aspect ratios in sub-100nm technologies is low yield. Another disadvantage is increased manufacturing costs. Also, the use of new low-k materials for dielectric layers is problematic in terms of process temperatures used in typical CMOS processes. Also, the scaling o...

AI Technical Summary

Problems solved by technology

[0003] The disadvantage of adopting trench capacitors with high aspect ratio in sub-100nm technology is low yield

Another disadvantage is increased manufacturing costs

Also, the use of new low-k materials for dielectric layers is problematic in terms of the process temperatures used in typical CMOS processes

Also, the scaling of trench capacitors and stack capacitors suffers from an increased risk of junction leakage, which has a negative effect on the memory effect

[0004] Another technical issue with scaling DRAM memory cells involves the cell transistors

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