Method for forming copper interconnected structure and CMP (Chemical Mechanical Polishing) equipment for same
A copper interconnection structure and equipment technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as low breakdown voltage, achieve device stability improvement, improve breakdown voltage, and improve implementation efficiency Effect
Active Publication Date: 2011-07-27
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0009] However, in the current multilayer interconnect structure composed of copper / low κ materials, there are still reliability problems such as low breakdown voltage, and its device stability still needs to be further improved, so it is still necessary to use copper / Improve the formation method of multilayer interconnection structure composed of low κ materials
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[0033] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.
[0034] In order to thoroughly understand the present invention, specific embodiments will be proposed in the following description, in order to illustrate how the present invention improves the problems existing in the prior art. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.
[0035] In the method for forming t...
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The invention provides a method for forming a copper interconnected structure and CMP (Chemical Mechanical Polishing) equipment for the same. The method comprises the following steps of: providing a silicon chip (8) obtained by using a copper chemical mechanical polishing method, wherein the silicon chip (8) is provided with a silicon substrate (10) and an interlaminar dielectric layer (12) covering the silicon substrate (10), the interlaminar dielectric layer (12) is provided with an interconnected groove and / or through hole with an upward opening, a copper metal (18) is embedded into the interconnected groove and / or through hole, a diffusion blocking layer (14) is arranged between the copper metal (18) and the interlaminar dielectric layer (12), and the interlaminar dielectric layer (12) is made of a dielectric material with the dielectric constant of 2.2-2.75; annealing the silicon chip (8); and cooling to form the copper interconnected structure.
Description
technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for forming a multilayer copper interconnection structure that can improve device stability. The invention also relates to a CMP device for carrying out the method. Background technique [0002] With the development of integrated circuit manufacturing technology, the requirements for the integration density of semiconductor devices are increasing. With the introduction of multi-layer metallization technology into the integrated circuit manufacturing process in the 1970s, the vertical space of the semiconductor wafer has been effectively utilized, and the integration level of the device has been significantly improved. Metallization is the process of depositing a metal film on an insulating dielectric film during chip manufacturing and then patterning it to form interconnected metal lines and hole-filling plugs for integrated circuits. For traditional...
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IPC IPC(8): H01L21/768H01L21/321
Inventor 邓武锋
Owner SEMICON MFG INT (SHANGHAI) CORP