Miniaturized on-chip antenna capable of resisting harmonic waves

Abstract

The invention discloses a miniaturized on-chip antenna capable of resisting harmonic waves, belonging to the technical field of wireless communication. The miniaturized on-chip antenna comprises a one-dimensional electromagnetic band gap structure and an on-chip dipole antenna, one end of the electromagnetic band gap is connected with the dipole antenna, the other end of the electromagnetic band gap is used as a differential feed end, and the electromagnetic band gap structure is of a one-dimensional differential slow wave structure and sequentially comprises a silicon substrate, a silicon dioxide and a metal top layer structure from the bottom up. The miniaturized on-chip antenna disclosed by the invention has higher integration property and can be prepared by adopting a standard CMOS (Complementary Metal Oxide Semiconductor) process and used for wireless interconnection for on-chip or chip-to-chip wireless data transmission.

Description

technical field [0001] The invention relates to a device in the technical field of wireless communication, in particular to a miniaturized on-chip antenna capable of suppressing harmonics. Background technique [0002] With the development of high-speed and radio-frequency integrated circuits, the chip speed is getting higher and higher, and the area is getting smaller and smaller. However, the problems of parasitic resistance, parasitic capacitance and parasitic inductance of traditional metal interconnection lines are becoming more and more serious. The resulting RC delay, IR Pressure drop, CV 2 f Power consumption and crosstalk between lines will become bottlenecks restricting the development of high-speed circuits and radio frequency circuits. Therefore, in recent years, wireless interconnection has been proposed as a solution to the limit problem of interconnection lines. For example, the on-chip wireless clock distribution system proposed and designed by B. A. Floyd ...

AI Technical Summary

Problems solved by technology

[0002] With the development of high-speed and radio-frequency integrated circuits, the chip speed is getting higher and higher, and the area is getting smaller and smaller. However, the problems of parasitic resistance, parasitic capacitance and parasitic inductance of traditional metal interconnection lines are becoming more and more serious. The resulting RC delay, IR Pressure drop, CV 2 f Power consumption and crosstalk between lines will become bottlenecks restricting the development of high-speed circuits and radio frequency circuits

Images