Preparation method of Through-Silicon-Via back coupling end

Abstract

The invention discloses a preparation method of a Through-Silicon-Via (TSV) back coupling end. The method comprises thinning a semiconductor substrate from the back side of the semiconductor substrate to make a TSV prepared in the semiconductor substrate in advance expose from the back of the semiconductor substrate, carrying out a chemically mechanical polishing towards the back of the semiconductor substrate to make the back surface of the TSV lower than that of the semiconductor substrate, forming an auxiliary metal layer on the back surface of the TSV, wherein the auxiliary metal layer and the main metal filling the TSV form a metal lamination composition on the back surface of the TSV, etching the back of the semiconductor substrate to make the metal lamination composition protrude from the back surface of the semiconductor substrate so as to form the TSV back coupling end. According to the invention, a recess effect of the chemically mechanical polishing technology is utilized to superpose the auxiliary metal layer on the back surface of the TSV in the modes of free mask and low temperature and the feasibility and yield of using the TSV to realize stacking and integration of multilayer microelectronic chips are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation and three-dimensional integration, in particular to a method for preparing a connection end at the back of a through-silicon hole. Background technique [0002] Three-dimensional integration technology uses Through-Silicon-Via (TSV) to realize the communication of multi-layer chips, which can effectively shorten the length of interconnection lines between chips and provide heterogeneous integration capabilities. It is an important direction for the development of microelectronics technology. . To achieve three-dimensional integration, three key technologies are required: preparation of through-silicon vias, chip thinning and transfer, and stacking and bonding. It is one of the core technologies to achieve three-dimensional integration to obtain an effective electrical connection between the back of the through-silicon via and another layer of chips. At present, it mainly relies ...

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Problems solved by technology

[0007] In view of this, the main purpose of the present invention is to propose a method for preparing the connection end on the back of the through-silicon via, so as to solve the problem that in the prior art, when the back of the chip includes rewiring layer processing and other processes, there is a high temperature process, which may make the temporary bond When the bond fails prematurely, and when the back of the substrate is directly etched and penetrates through silicon vias, the subsequent bonding process has high requirements for temperature and surface flatness, and the yield is difficult to guarantee, etc.

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