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Signal stability detector and time delay tester

A technology of delay testing and stability, applied in the field of semiconductor technology, can solve the problems of large circuit design complexity and hardware overhead, and achieve the effect of low overhead

Active Publication Date: 2013-04-03
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

Therefore, adopting this method will bring great circuit design complexity and hardware overhead

Method used

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  • Signal stability detector and time delay tester
  • Signal stability detector and time delay tester
  • Signal stability detector and time delay tester

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Embodiment Construction

[0025] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0026]A complete delay test requires the ability to verify that the propagation delay of any path in the circuit under test exceeds the operating clock period. A path here is a physical path in a combinational circuit, that is, an alternating sequence of leads and gates from the original input of the circuit or the output of the flip-flop to the original output of the circuit or the input of the flip-flop. Since the propagation delays of the rising transition signal and the falling transition signal in the circuit elements are different, each physical path corresponds to two logical pa...

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Abstract

The invention provides a signal stability detector and a time delay testing device using the signal stability detector. The time delay test device is provided with a corresponding signal stability detector at each key combinational logic output point, which is used to detect whether the output signal of each key combinational logic point is reversed in the stable phase of the combinational logic signal ; and a global error signal generator is set, which is used to generate a global error signal when any signal stability detector detects that the combinational logic signal flips within the detection range, and is used to indicate the timing failure of the circuit. In order to effectively support the off-line delay test, a local scan enable signal generator is also applied in the scan chain of the circuit. The time delay testing device can effectively perform online time delay fault detection, and can provide effective support for offline time delay fault detection, and the hardware cost is relatively low.

Description

technical field [0001] The invention belongs to the technical field of semiconductor technology, and in particular relates to, in a high-performance chip, effectively detecting the delay fault in the chip to ensure the performance and reliability of the chip. Background technique [0002] With the development of integrated circuit manufacturing technology, the feature size of transistors has been continuously refined. The complexity and level of integration of the entire chip continues to increase. It is becoming more and more obvious that chips contain various defects after they are manufactured, and thus pose serious challenges to the performance and reliability of chips. In addition, under the deep submicron process, it is difficult to accurately control the process parameters in the integrated circuit to the corresponding expected value, but there is a process deviation. As a result, there will be a large time delay deviation in the logic gates and signal propagation p...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3177
Inventor 裴颂伟李华伟李晓维
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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