Semiconductor package realizing connection by connecting sheets and manufacturing method for semiconductor package

Abstract

The invention discloses a semiconductor package body realizing internal connection by connecting sheets. The semiconductor package body comprises a plurality of chips, a plurality of substrates, the connecting sheets and a plastic package body, wherein each chip has a plurality of top contact areas and a plurality of bottom contact areas; the substrates are used for accommodating the chips; the bottom contact areas of the chips are electrically connected with the substrates; the substrates are provided with a plurality of substrate outer pins; the connecting sheets are connected with the plurality of chips and the plurality of correspondingly distributed top contact areas of the plurality of chips so as to fix the plurality of chips; the ends of the connecting sheets are used as pins of the chips and connected with the exterior; and the plastic package body is used for packaging the chips, the substrates and the connecting sheets. In the process, one or more connecting sheets are fixedly connected with the plurality of chips and then packaged; and the connecting sheets are separated by cutting or grinding the top of the package finally. Due to the fixed connection of the connecting sheets, the influence of the dislocation of the chips on the circuit performance of the chips during manufacturing can be avoided.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a manufacturing method, in particular to a semiconductor packaging and a manufacturing method thereof which are connected by connecting sheets. Background technique [0002] In order to meet the needs of miniaturization of electronic products, multi-chip semiconductor packaging has become a trend, and the semiconductor packaging of multi-chip modules carries multiple chips in a single package. [0003] For example, in the Chinese patent authorization announcement number CN201063342Y, a multi-chip packaging structure is disclosed, including: a first lead frame, including a first chip seat, a first inner pin and a second outer pin; a second lead frame, including a first Two chip seats and second inner pins; the second lead frame is located above or below the first lead frame, and the first lead frame is electrically connected to the second lead frame through the connector; the first chip is...

AI Technical Summary

Problems solved by technology

[0005] The above-mentioned prior art for chip packaging is to use wires for the connection between the chip and the lead frame, but in the packaging process of multiple chips connected by wires, the bonding and soldering reflow process usually make the chips prone to error. Movement, and due to the movement of the chip, a short circuit between the wires is caused at the same time, which affects the performance of the circuit. In addition, in the prior art, in order to increase the pins, cutting is performed at the bottom of the package, which has poor flexibility and increases the complexity of the process. , is not conducive to reducing production costs

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