Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

Method for regulating back gate threshold voltage of SOI-NMOS (silicon on insulator-N-channel metal oxide semiconductor) device

A technology of SOI-NMOS and threshold voltage, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device testing/measurement, circuits, etc., can solve the problem of inaccurate control of the range, inaccurate control of doping concentration, increase in process complexity, etc. question

Inactive Publication Date: 2011-11-16
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
View PDF2 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

To increase the threshold voltage of the back gate by doping the back gate channel, first of all, the range of the threshold voltage increase cannot be precisely controlled, because the doping concentration cannot be precisely controlled; in addition, this will increase the complexity of the process, increase the cost of manufacturing, and doping Miscellaneous processes (such as ion implantation) can cause damage to the device and produce other effects

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for regulating back gate threshold voltage of SOI-NMOS (silicon on insulator-N-channel metal oxide semiconductor) device
  • Method for regulating back gate threshold voltage of SOI-NMOS (silicon on insulator-N-channel metal oxide semiconductor) device
  • Method for regulating back gate threshold voltage of SOI-NMOS (silicon on insulator-N-channel metal oxide semiconductor) device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0022] Such as figure 1 as shown, figure 1 It is an SOI-NMOS device that can be used in the present invention. The SOI silicon wafer comprises a top silicon film (1), an insulating oxide layer (2) and a silicon substrate (3), and an SOI-NMOS device is prepared on the top silicon film (1). The SOI material is a commercial conventional oxygen ion implantation isolation (SIMOX) sheet, and other thermal bonding and smart-cut (Smart-Cut) sheets can also be used. For a normal SOI-NMOS device, the gate and drain are connected to the power supply potential (Vdd), and the source and back gate are connected to the ground potential (Vss).

[0023] Bulk silicon NMOS devices in the prior art generally have only three terminals, namely: gate, source and drain, and only focus on the threshold voltage of the gate. The general method for ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a method for regulating back gate threshold voltage of an SOI-NMOS (silicon on insulator-N-channel metal oxide semiconductor) device. The method comprises the following steps: improving the back gate threshold voltage and lowering the back gate threshold voltage, wherein the method for improving the back gate threshold voltage comprises: grounding potential for a grid electrode, a drain electrode and a source electrode of the SOI-NMOS device; and connecting the positive direct current voltage with the absolute value greater than 80V to a back grid electrode of the SOI-NMOS device for more than 10 seconds; and the method for lowering the back gate threshold voltage comprises: grounding potential for the grid electrode, the drain electrode and the source electrode of the SOI-NMOS device; and connecting the negative direct current voltage with the absolute value greater than 80V to a back grid electrode of the SOI-NMOS device for more than 10 seconds. The threshold voltage of back grid channel start of the SOI-NMOS device is regulated, and the increase of the back gate threshold voltage and the decrease of off leakage current of the SOI-NMOS device can be realized.

Description

technical field [0001] The invention relates to the technical field of SOI CMOS semiconductor integrated circuits, in particular to a method for adjusting the back gate threshold voltage of an SOI-NMOS device. Background technique [0002] SOI (Silicon-On-Insulator) technology refers to the fabrication of devices and circuits on a silicon film on an insulating layer (BOX), which is different from the ordinary bulk silicon technology that directly manufactures devices and circuits on a semiconductor substrate. Complete dielectric isolation is achieved between devices, so SOI-CMOS integrated circuits essentially avoid the latch-up effect of bulk silicon CMOS circuits; in addition, SOI devices have small short-channel effects, can naturally form shallow junctions, and leak current Small, with excellent subthreshold characteristics. SOI-CMOS integrated circuits with no latch, high speed, low power supply voltage, low power consumption, radiation resistance and high temperature ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/66
Inventor 梅博毕津顺韩郑生
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com