Method for manufacturing grid electrode of semiconductor device

Abstract

The invention discloses a method for manufacturing a grid electrode of a semiconductor device. The method comprises the following steps: a) forming a first grid oxide layer, a grid electrode material layer, a second grid oxide layer, a first hard mask layer, a second hard mask layer, an anti-reflection coating layer and a photo-etching glue layer having a pattern on a front-end device layer in turn; b) etching the anti-reflection coating layer; c) etching the second hard mask layer; d) etching the first hard mask layer; and e) etching the second grid oxide layer, the grid electrode material layer and the first grid oxide layer in turn by taking the first hard mask layer as a mask, and then removing the first hard mask layer, thereby forming the grid electrode, wherein the method also comprises a step of introducing an etching gas for finishing a to-be-finished layer. The method provided by the invention can be used for promoting the property, reliability and yield of a device.

Description

Technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a gate of a semiconductor device. Background technique [0002] With the gradual increase in the demand for high integration and high performance of VLSI, semiconductor technology is developing towards technology nodes with 45nm or smaller feature sizes. Correspondingly, the requirements for precise control of semiconductor device manufacturing are getting higher and higher to ensure that the products meet the design requirements and improve the yield rate. [0003] The formation of the gate in the transistor is a critical step in the semiconductor manufacturing process. The reason is that the gate is the smallest physical size structure in the entire integrated circuit manufacturing process. Therefore, the critical dimension (CD) of the gate often requires precise control. A large number of technical improvements have been devoted to improving the acc...

AI Technical Summary

Problems solved by technology

If the LES is too large, it indicates that the etching deviation of the key dimension of the gate in the vertical direction is relatively large, that is, the gate shortens seriously in the vertical direction after etching

This may prevent the gate from overlapping with the active area, resulting in reduced device performance and reliability, lower yield, and problems such as leakage in the device and critical dimension limitations.

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