risc microprocessor instruction decoding circuit

Abstract

The invention discloses a RISC microprocessor instruction decoding circuit, the instruction comparator compares the instruction code field and the target instruction code; the 64-bit instruction register in the instruction buffer is used to temporarily store the instruction currently waiting for decoding, and the instruction length is 7 bits The register is used to record the number of instruction bits contained in the current instruction register; the operand selector outputs the immediate field to the fetch unit, and the immediate field and register field to the execution unit; the instruction counter counts 1 in the first 4 bits of the input instruction The number, plus the number of subsequent bytes required by the I bit is the total number of bytes of the current instruction; the instruction shifter uses the output of the instruction counter as an input parameter, and performs 64-bit instructions according to the contents of the 7-bit instruction length register. The input instruction data in the register is shifted to the left, and merged with the input instruction in the 64-bit instruction register after shifting. The invention has the advantages of simple circuit structure, small scale and few stages, and can remarkably improve the performance of the RISC microprocessor.

Description

technical field [0001] The invention relates to the field of microprocessors, in particular to a RISC (Reduced Instruction Set Computer) microprocessor instruction decoding circuit. Background technique [0002] The current design of VLSI (Very Large Scale Integration) and SOC (System on Chip) cannot do without the core component of the central microprocessor. The central microprocessor is the brain of the entire SOC chip, and all peripheral device drivers and operating system codes are interpreted and executed by it. And all these software codes, no matter what kind of high-level language (C, C++, Java) is used to write, will eventually be compiled into machine instructions, and are fetched, decoded and executed by the central microprocessor. [0003] Most of the central microprocessors used in system-on-chip design are provided in the form of IP (intellectual property rights), and its main suppliers include ARM and MIPS companies in the United States. The central micropr...

AI Technical Summary

Problems solved by technology

In the case of no system design for the instruction structure in the early stage, the decoding structure will only become more and more complex, and the scale of the decoding circuit will become larger and larger

The complexity of the decoding structure will cause the main frequency of the RISC microprocessor to be unable to increase quickly, which can only be realized by increasing the number of pipeline stages of the decoding circuit, which will cause a series of other problems such as a larger jump instruction execution delay. question

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