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Memory and Sense Amplifiers

A technology for sensitive amplifiers and control terminals, applied in the field of memory and sensitive amplifiers, can solve the problems of unreadable and slowed memory reading speed, and achieve the effects of reducing pre-charging time, increasing reading speed, and enhancing channel conductivity

Active Publication Date: 2015-11-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] The invention solves the problem that the reading speed of the memory in the prior art is reduced due to the reduction of the working voltage, or even cannot be read.

Method used

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  • Memory and Sense Amplifiers
  • Memory and Sense Amplifiers
  • Memory and Sense Amplifiers

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] see image 3 As shown, the sense amplifier provided in this embodiment includes: a precharge unit 11 , a bit line adjustment unit 12 , a current mirror unit 13 , a comparison unit 14 , a bias unit 16 and an output unit 15 .

[0048] The pre-charging unit 11 charges the data line d1 when the bit line is pre-charged (before reading the memory cell), that is, increases the voltage of the data line node VE (data line voltage).

[0049] The pre-charging unit 11 includes a pre-charging transistor m P , precharge transistor m P The gate is input with the precharge control signal PRE, the source is input with the working voltage source VDDQ, and the drain is connected to the data line node VE (or in other words, connected to the data line dl), that is, the output data line voltage.

[0050] The bit line adjustment unit 12, when the bit line is precharged, feeds back and amplifies the voltage of the bit line node VD (bit line voltage) to obtain a feedback voltage. Under the co...

Embodiment 2

[0064] see Figure 4 As shown, the structure of the sense amplifier provided in this embodiment is substantially the same as that of the sense amplifier in Embodiment 1, and the difference is that the bit line adjustment unit 12 includes: a regulated power supply Vreg, a feedback transistor m10, an impedance transistor m11 and an adjustment transistor m2. The feedback transistor m10 , the impedance transistor m11 and the adjustment transistor m2 all include a control terminal (gate), a first terminal (source) and a second terminal (drain). The output terminal of the regulated power supply Vreg is connected to the first terminal of the feedback transistor m10, and the regulated power supply Vreg provides the first terminal of the feedback transistor m10 with a value range including: 0.8V~2V working voltage; the second terminal of the feedback transistor m10 Connect the feedback node VC, that is, output the feedback voltage; the control terminal of the feedback transistor m10 i...

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Abstract

A memory and a sensitive amplifier, the sensitive amplifier includes a current mirror unit, the current mirror unit includes: an input transistor with a control terminal, a first terminal and a second terminal, the second terminal of which is connected to a data line node, and the first terminal of which connected to a voltage source; a mirror transistor having a control terminal, a first terminal and a second terminal, the second terminal of which is connected to the data node, the first terminal of which is connected to the voltage source, and the control terminal of which is connected to the control terminal of the input transistor; the first impedance element, Its first end is connected to the second end of the input transistor, and the second end of the first impedance element is connected to the control end of the input transistor; the pull-up current source, one end of which is connected to the first end of the first impedance element, and the other end is connected to the voltage source; a pull-down current source, one end of which is connected to the second end of the first impedance element, and the other end is grounded, and the current value of the pull-down current source is equal to the current value of the pull-up current source. The sensitive amplifier of the invention improves the reading speed of the memory under the lower operating voltage source.

Description

technical field [0001] The invention relates to a memory circuit, in particular to a memory and a sensitive amplifier. Background technique [0002] Sensitive amplifier (SA, SenseAmplifier) ​​is an important part of the memory, which directly affects the reading speed of the memory. Sense amplifiers sense small signal changes on bit-lines and amplify the small signal changes to obtain data stored on memory cells. Before sensing small signal changes on the bit-line, the bit-line adjustment unit of the sense amplifier will adjust the bit-line voltage to a fixed value, so that the bit-line voltage can be stabilized as soon as possible, and then it can sense a stable voltage when reading. bit line current. [0003] figure 1 It is a circuit diagram of an existing sensitive amplifier of a memory, including: [0004] The precharge unit 11 charges the data line node when the bit line is precharged, including: a precharge transistor mp, whose control terminal (gate) is connected ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/06G11C7/12
Inventor 杨光军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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