A superjunction vertical double diffused n-type metal oxide semiconductor transistor

Abstract

The invention discloses a superstructural longitudinal double-diffusion N-type metal oxide semiconductor tube. The superstructural longitudinal double-diffusion N-type metal oxide semiconductor tube comprises one or more tube units, wherein the tube unit comprises a drain metal; a heavily doped N-type silicon substrate which is used as a drain region is arranged on the drain metal; an N-type doped epitaxial layer is arranged on the silicon substrate; a P-type doped columnar semiconductor region is arranged in the epitaxial layer; a P-type doped semiconductor body region is arranged on the columnar semiconductor; an N-type heavily doped semiconductor source region and a P-type heavily doped semiconductor contact region are arranged in the body region; the P-type heavily doped semiconductorcontact region is cross-shaped; and the cross-shaped P-type heavily doped semiconductor contact region divides the N-type heavily doped semiconductor source region into four blocks which are disconnected from one another. In the structure, the opening possibility of a parasitic triode is reduced without affecting the on-resistance performance of an apparatus and increasing manufacturing steps of a process and the degree of difficulty, so that the avalanche tolerance of the apparatus is improved and the reliability of the apparatus when the apparatus works in a severe weather is further ensured.

Description

technical field [0001] The invention relates to the field of power semiconductor devices, in particular to a silicon-made high-voltage superjunction vertical double-diffusion N-type metal oxide semiconductor field effect transistor. [0002] Background technique [0003] At present, power devices are more and more widely used in daily life, production and other fields, especially power metal oxide semiconductor field effect transistors, because they have faster switching speed, smaller drive current, and wider safe operating area , so it has been favored by many researchers. In brushless motors, motor drives, and automotive electronics, a class of typical applications for power Mosfets, the driven loads are mostly inductive, and some topologies inevitably operate in unclamped Inductive switching conditions, thus bringing the possibility of working in an avalanche state. On the other hand, with the reduction of the chip area and the increase of the switching frequency, the...

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Problems solved by technology

When the avalanche hole current enters the P-type body region and flows under the N-type source region, a voltage drop is formed on the base resistance of the parasitic transistor. If the voltage drop is greater than the turn-on voltage of the PN junction, the parasitic transistor is turned on. This can easily lead to secondary breakdown of the device

[0004] However, referring to Figure 7 , the N-type source region and the P-type body contact region in the traditional super-junction vertical double-diffusion N-type metal oxide semiconductor transistor are strip layouts, and the hole current can only pass through the P-type body contact region below the N-type source region. Figure 8 , it is easy to make the voltage drop between the P-type body contact region and the N-type source region reach the turn-on voltage of the parasitic transistor, and then fail

The traditional method of improving the avalanche durability of power metal oxide semiconductor field effect transistors is only suitable for low current density; when the current density is further increased, it will still lead to the conduction of the parasitic transistor inside the power metal oxide semiconductor field effect transistor

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