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Magnetic random access memory cell array, memory and reading/writing method thereof

A random access memory, random storage technology, applied in static memory, digital memory information, information storage and other directions, can solve the problem that MRAM array cannot provide Rashba storage unit read and write separation mechanism, cannot effectively support Rashba storage unit read and write operations, devices The problem of high working noise, etc., achieves the effect of fewer production processes, increased data writing speed, and reduced device power consumption

Active Publication Date: 2012-01-11
INST OF PHYSICS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problems of the former are that the device is noisy, the integration density is low, and the process is difficult.
[0006] The above two types of MRAM arrays cannot provide the read-write separation mechanism required by the Rashba storage unit, and cannot effectively support the read and write operations of the Rashba storage unit.

Method used

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  • Magnetic random access memory cell array, memory and reading/writing method thereof
  • Magnetic random access memory cell array, memory and reading/writing method thereof
  • Magnetic random access memory cell array, memory and reading/writing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0066] According to Embodiment 1 of the present invention, a magnetic random access memory (MRAM) array based on the Rashba effect is provided. FIG. 2(a) exemplarily shows a planar wiring diagram of a 2×2 memory cell array. With reference to Fig. 2 (a), this 2 * 2 storage cell array can realize larger-scale two-dimensional storage array along X, Y direction expansion, if this planar array is along Z direction (that is, perpendicular to X, the plane that Y constitutes The direction of) expansion can realize three-dimensional storage array. The bottom layer of each memory cell occupies a transistor T, and in this embodiment, two transistors T share a source. From the perspective of actual device technology, the MRAM array needs to be prepared layer by layer (generally, layer by layer from bottom to top). In this embodiment, the functional units of the MRAM array are distributed on the first to sixth layers. The specific layout design of this embodiment will be described below ...

Embodiment 2

[0082] According to Embodiment 2 of the present invention, a magnetic random access memory (MRAM) array based on the Rashba effect is provided. FIG. 3(a) exemplarily shows a planar wiring diagram of a 2×2 memory cell array. With reference to Fig. 3 (a), this 2 * 2 storage cell array can realize larger-scale two-dimensional storage array along X, Y direction expansion, if this planar array is along Z direction (that is, perpendicular to X, the plane that Y constitutes The direction of) expansion can realize three-dimensional storage array. The bottom layer of each memory cell occupies a transistor T, and in this embodiment, two transistors T share a source. From the perspective of actual device technology, the MRAM array needs to be prepared layer by layer (generally, layer by layer from bottom to top). In this embodiment, the functional units of the MRAM array are distributed on the first to fifth layers. The specific layout design of this embodiment will be described below ...

Embodiment 3

[0092] According to an embodiment of the present invention, an MRAM memory is provided, and the MRAM memory includes an MRAM memory cell array and a read / write circuit. Wherein, the MRAM memory cell array can be the MRAM memory cell array described in Embodiment 1 or 2.

[0093] Such as Figure 4A As shown, this embodiment provides a read-write circuit based on the memory array of Embodiment 1 or 2. Figure 4A Among them, BL is the abbreviation of BitLine (bit line), and the letter x represents the number 0, 1, 2, 3...etc., BLx represents BL0, BL1, BL2, BL3,..., BL15 equipotential lines. Similarly, BLx' stands for BL0', BL1', BL2', BL3',..., BL15' equipotential line, SL is the abbreviation of SourceLine (source line), SLx stands for BL0, BL1, BL2, BL3 ,..., SL15 and other source lines. Bx and Bx' are the general designation of all control bit lines BitLine conduction signal lines in the read-write circuit. Bx represents B0, B1, B2, B3, . . . , B15. Bx' stands for B0', B1...

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Abstract

The invention provides a magnetic random access memory, comprising a magnetic random access memory cell array and a reading / writing circuit thereof. The magnetic random access memory cell array comprises a transistor array distributed on a first layer, transistor sources and drains on a second layer, source lines and drain output electrodes on a third layer, non-magnetic metal lines on a fourth layer, magnetic tunnel junctions arranged on the upper surfaces of the non-magnetic metal line, and a first bit line and a second bit line on a layer above the magnetic tunnel junctions, wherein the first bit lines are in contact with top electrodes of the magnetic tunnel junctions, the second bit lines are communicated with the non-magnetic metal lines through conducting holes, the third layer is in direct contact with the fourth layer, and spacing layers are respectively arranged among the rest layers. The invention also provides a corresponding reading / writing method. The magnetic random access memory cell array provided by the invention has a reading / writing separation system, can favorably supporting a Rashba memory cell, is beneficial to increase of memory density, reduction of device power consumption and increased of data writing / in speed and reliability, and has the advantages of fewer manufacturing procedures and simpler process.

Description

technical field [0001] The invention relates to the technical field of magnetic random access memory, in particular, the invention relates to a magnetic random access memory unit array, a magnetic random access memory and a reading and writing method thereof. Background technique [0002] Memory has gone through several generations of changes since its inception. The memory commonly used at present is mainly the CMOS circuit that appeared in the 1980s. Combining single-tube circuits and 45nm line width and other technologies, the integration density of current memories, especially DRAMs, can reach GB levels. However, in the exploration of higher density and lower power consumption of memory, the existing DRAM based on CMOS circuit technology is restricted by a series of problems: especially short channel effect, leakage current and volatility, etc. question. On the other hand, the proposal of Giant Magneto Resistance (GMR) and Tunneling Magneto Resistance (TMR) provides p...

Claims

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Application Information

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IPC IPC(8): G11C7/06G11C11/16
CPCG11C11/1653G11C11/1659G11C11/1673G11C11/1675G11C11/1693
Inventor 王译李海韩秀峰
Owner INST OF PHYSICS - CHINESE ACAD OF SCI
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