Method for realizing conflict-free real-time data access in FPGA (field programmable gate array)

A data and real-time technology, applied in electrical digital data processing, instruments, etc., can solve problems such as data errors and dislocations, achieve accurate access, low cost, and meet application requirements.

Inactive Publication Date: 2012-01-25
NARI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0006] Two-level buffers are used as data pools in FPGA, which are first-level buffers and second-level buffers. Two first-level buffers and second-level buffers with the same or different capacities are used, as well as buffers that describe the information an

Method used

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  • Method for realizing conflict-free real-time data access in FPGA (field programmable gate array)
  • Method for realizing conflict-free real-time data access in FPGA (field programmable gate array)

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[0016] The present invention will be further described below in conjunction with the accompanying drawings. The following examples are only used to illustrate the technical solution of the present invention more clearly, but not to limit the protection scope of the present invention.

[0017] figure 1 It is a functional block diagram of the data conflict-free real-time access method implemented in FPGA. FPGA includes a primary buffer and a secondary buffer. The secondary buffer is divided into multiple data areas, and the size and number of blocks can be configured according to actual use. .

[0018] Taking reception as an example, the decoder in synchronous serial communication recovers the original data and clock from the received code stream according to the actual line code pattern, and converts the serial input data into parallel data under the control of the clock. Or combine the parallel input data into parallel data with a larger width and save it in the FIFO of the ...

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Abstract

The invention discloses a method for realizing conflict-free real-time data access in an FPGA (field programmable gate array). In the FPGA, a two-stage buffer is used as a data pool, namely a first-stage buffer area and a second-stage buffer area. The method comprises the following steps of: receiving serial data output by an optical receiver and storing effective data by the first-stage buffer area; and transferring all data in the first-stage buffer area to the second-stage buffer area by using an idle time accessed by the second-stage buffer area. Based on the two-stage buffer and a buffer area descriptor, the conflict-free real-time interaction and data access between asynchronous data links in the FPGA are realized.

Description

technical field [0001] The invention relates to a synchronous serial communication carried out by optical fiber for relay protection equipment of a power system, which belongs to the technical field of industrial communication. Background technique [0002] Power system relay protection equipment is an automatic device that quickly and accurately trips the circuit breaker or sends a signal when the electrical components in the power system fail or operate abnormally. Electronic current transformers and electronic voltage transformers widely used in smart substations make the interconnection between microcomputer relay protection equipment and these primary equipment change from traditional cable transmission of analog to digital signal transmission using optical fiber communication. Therefore, optical fiber communication technology It has become one of the basic technologies to realize modern relay protection equipment. [0003] The optical fiber communication between the e...

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Application Information

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IPC IPC(8): G06F13/40
Inventor 姚吉文周华良姜雷夏雨胡钰林
Owner NARI TECH CO LTD
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