Non-carrier semiconductor packaging part and manufacturing method thereof
A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as delamination moisture, short circuit, infiltration, etc., to avoid weak bending and reduce manufacturing costs , Increase the effect of adhesion
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no. 1 example
[0076] see Figure 3A to Figure 3I , which is a schematic view of the first embodiment of the submountless semiconductor package and the manufacturing method thereof of the present invention.
[0077] Such as Figure 3A As shown, a metal carrier 30 such as a copper plate is prepared, and the metal carrier 30 has a first surface 30a and a second surface 30b opposite to each other.
[0078] Such as Figure 3B As shown, a patterned first resistance layer 31a is then formed on the first surface of the metal carrier 30, so that the patterned first resistance layer 31a defines the electrical terminals and chip pad positions, and is placed on the metal carrier 30 The second surface is covered with a second resistance layer 31b, and the first and second resistance layers are, for example, dry films.
[0079] Such as Figure 3C As shown, a part of the metal carrier that is not covered by the first resistive layer 31a is removed by a half-etching process, thereby forming a plurality...
no. 2 example
[0094] see Figure 4 , which is a schematic view of the second embodiment of the submountless semiconductor package and the manufacturing method thereof of the present invention.
[0095] This embodiment is substantially the same as the previous embodiments, the main difference is that the semiconductor chip can also be electrically coupled to the connection pads on the metal block through a metal bump in a flip-chip manner.
[0096] The semiconductor chip 43 of this embodiment is connected on the connection pad 48 in a flip-chip (Flip-Chip) manner; The solder bump 49 is electrically coupled to the connection pad 48 on the metal bump.
[0097] Compared with the structure of connecting the semiconductor chip and the connection pad with the bonding wire, the flip-chip technology using the bump can further shorten the electrical connection path between the semiconductor chip and the connection pad, and can better ensure the electrical performance between the semiconductor chip a...
no. 3 example
[0099] see Figure 5A to Figure 5C , which is a schematic diagram of a third embodiment of the submountless semiconductor package and its manufacturing method of the present invention.
[0100] This embodiment is substantially the same as the first embodiment, the main difference is that it also includes the preparation of build-up traces.
[0101] First, according to Figure 3A to Figure 3F step, forming a plurality of grooves 301 and corresponding metal blocks 302 on the first surface of the metal carrier 30, filling the first colloid 35a in the grooves 301, and exposing the metal blocks 302 after the first colloid 35a A conductive layer 37 such as thin copper is formed on the first colloid 35 a and the upper surface of the metal block 302 by means of electroless plating or sputtering. Next, a patterned third resistance layer 31c is formed on the conductive layer 37, so that the patterned third resistance layer 31c is formed with a plurality of openings 310c to define the ...
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Abstract
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