Device for debugging wafer-level test scheme under final test environment of automatic test device
A technology of automatic test device and test scheme, which is applied in the semiconductor field, can solve the problems of time-consuming and difficult to provide probe cards, etc., and achieve the effect of simple structure, convenient development and debugging, and short debugging time period
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0037] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention will be further elaborated below.
[0038] Figure 1 to Figure 7 A schematic structural view of the testing device of the present invention is shown. The test device consists of the following parts from bottom to top:
[0039] Automatic Test Equipment (ATE)1,
[0040] Chip test board 2 (Wafer Prober Interface, hereinafter referred to as WPI board); installed on the ATE1, figure 2 for the schematic diagram.
[0041] Test pogo pin ring 3 (hereinafter referred to as Pogo Tower), installed on the WPI board 2; image 3 for the schematic diagram.
[0042] Probe Card 4 (Probe Card, referred to as PC), installed on the Pogo Tower3, fixed with screws; Figure 4 for the schematic diagram.
[0043] Probe ring 5 (hereinafter referred to as Pogo ring), used for debugging, aligns through the screw mounting holes of probe c...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com