Bonding pad planarization process for improving packaging feasibility of bump structure

A flattening process and bonding pad technology, which is applied in the manufacturing of electrical components, electrical solid state devices, semiconductor/solid state devices, etc., can solve the problem that it is difficult to reduce bumps 16, etc., to increase feasibility and yield, and improve flatness Effect

Inactive Publication Date: 2012-05-16
RICHTEK TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The rear passivation layer 14 is very thick, so it is difficult to reduce the problems caused by the uneven surface of the aforementioned bump 16
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Method used

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  • Bonding pad planarization process for improving packaging feasibility of bump structure
  • Bonding pad planarization process for improving packaging feasibility of bump structure
  • Bonding pad planarization process for improving packaging feasibility of bump structure

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Embodiment Construction

[0022] Figure 4A to Figure 4H It is a flowchart of the first embodiment of the present invention. After completing the front-end process of the wafer, such as Figure 4A As shown, the wafer passivation layer 12 and the rear passivation layer 14 cover the wafer, exposing only the bonding pads 10, which are usually aluminum. When making a bond pad, such as Figure 4B As shown, the barrier layer 262 and the seed layer 264 are sequentially sputtered. The barrier layer 262 can be titanium (Ti), titanium tungsten (TiW) or chromium (Cr), with a thickness between The seed layer 264 can be copper (Cu) or gold (Au), with a thickness between So far it is the same as conventional technology. Then a thick metal layer 30 of copper or gold is electroplated on the seed layer 264 to become Figure 4C structure shown. Preferably, the thickness of the thick metal layer 30 is greater than 3 μm. Then chemical mechanical polishing (CMP) the surface of the thick metal layer 30 becomes Fi...

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Abstract

The invention provides a bonding pad planarization process for improving packaging feasibility of a bump structure. The process comprises the following steps of: after forming a thick metal layer above a bonding pad, etching the thick metal layer to form a planarized metal film; and growing a bump on the planarized metal film above the bonding pad. By using the bonding pad planarization process provided by the invention, the smoothness of the bump can be largely improved so that the feasibility and yield of the packaging process are enhanced.

Description

technical field [0001] The present invention relates to a wafer manufacturing process, in particular to a bumping process of wafer-level packaging (wafer-level assembly), and is a bonding pad planarization process for improving the feasibility of bump structure packaging. Background technique [0002] In wafer-level packaging, the coplanarity after electroplating is not good due to the topography of the wafer surface or the coating of the post-passivation layer (re-passivation layer), and the poor coplanarity will cause subsequent wire bonding packaging or Difficulty in press-fit packaging. As shown in Figure 1, the traditional flip-chip process is to directly grow bumps 16 on the aluminum pad 10, and the edge of the aluminum pad 10 has a cliff formed by the wafer passivation layer 12 and the rear passivation layer 14, so after electroplating, There are towering protrusions 18 on the edge of the bump 16 . When the bump 16 is used in wire bonding packaging, as shown in FIG....

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Application Information

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IPC IPC(8): H01L21/60H01L23/00
CPCH01L24/11H01L2224/48463H01L2224/11H01L2924/00012
Inventor 陈柏瑞杨玉林
Owner RICHTEK TECH
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