Single chip microcomputer hardware simulator and simulation method for same

A technology of hardware simulation and emulation method, which is applied in the direction of detecting faulty computer hardware and function inspection, etc. It can solve the problems of being unable to quickly and accurately grasp embedded system methods and techniques, and cannot fully simulate, so as to facilitate embedded development Design, facilitate hardware simulation, and enhance the effect of experimental results

Active Publication Date: 2012-06-20
广州市风标电子技术有限公司
View PDF2 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of software simulation is that it cannot fully simulate the hardware-related parts, so the final design must be completed through hardware simulation
This kind of separation of software and hardware has brought many adverse ef

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Single chip microcomputer hardware simulator and simulation method for same
  • Single chip microcomputer hardware simulator and simulation method for same
  • Single chip microcomputer hardware simulator and simulation method for same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] The invention builds a single-chip hardware emulation system in which a virtual circuit on a PC interacts and synchronizes with an actual hardware circuit based on a hardware emulator.

[0028] refer to figure 1 , The single-chip microcomputer hardware emulator of the present invention includes a processor for emulation control, and the data port of the processor is respectively connected with a USB interface circuit and an output emulation head.

[0029] preferred, see figure 2 , processor is STM32F103 controller among the present invention, and its periphery is connected with the quartz oscillator SX1 that provides clock frequency and SC1, SC2, and all the other ports are respectively connected to such as image 3 The output shown in the emulation header and Figure 4 The USB interface circuit shown.

[0030] refer to Figure 5 and Figure 6 , a single-chip microcomputer hardware simulation method, comprising the following steps:

[0031] Run the Proteus softwa...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a single chip microcomputer hardware simulator and a simulation method for the same. The simulation method includes the steps: operating a Proteus software on a PC (personal computer) to perform software simulation for a virtual circuit, and selecting a corresponding simulation model during software simulation; utilizing the simulation model to logically process digital level signals of pins of a master controller in the virtual circuit and signals acquired by the single chip microcomputer hardware simulator, and packing the processed signals into a data packet; transmitting the data packet into the single chip microcomputer hardware simulator through a USB (universal serial bus) interface; enabling the single chip microcomputer hardware simulator to receive the data packet from the simulation model and drive an output simulation head to output signals; and enabling a hardware circuit to respond the signals from the simulation head so that hardware simulation is completed. The simulation method realizes interaction and synchronization of the virtual circuit and the practical hardware circuit, so that experimental effect of experimental training equipment is enhanced, and study of students and embedded development and design of developers are facilitated.

Description

technical field [0001] The invention relates to the field of single-chip computer simulation, in particular to a single-chip computer hardware simulator and simulation method based on Proteus software. Background technique [0002] In the design of embedded systems, the scope of simulation applications mainly focuses on the simulation of programs. For example, in the development process of single-chip microcomputer, program design is the most important but also the most difficult. Traditional embedded system simulation software, such as Proteus, has little relationship with embedded hardware systems. Software emulation is pure software emulation and has nothing to do with the hardware system. The disadvantage of software simulation is that it cannot fully simulate the hardware-related parts, so the final design must be completed through hardware simulation. This separation of software and hardware has brought many adverse effects on students and staff learning embedded sy...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F11/26
Inventor 匡载华
Owner 广州市风标电子技术有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap