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Parallel multiprocessor computer design method

A multi-processor and design method technology, applied in the computer field, can solve problems such as host failure and low operating efficiency, and achieve high computing efficiency and availability

Active Publication Date: 2012-06-27
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0005] The current common practice is to use the method of software virtual partitioning, that is, install virtualization software on the operating system of a computer to virtualize multiple operating systems, but this method is based on the same hardware system and parent operating system, and the operating efficiency is relatively low. Low, once there is a problem with the hardware or the parent operating system, the multiple hosts running on it will all fail

Method used

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  • Parallel multiprocessor computer design method

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Embodiment

[0038] The design method of the parallel multiprocessor computer of the present invention proposes a new computer architecture based on NUMA, and provides a method for partitioning a multiprocessor computer. Users can set computer partitions by themselves according to business needs. The divided partitions are completely independent physically.

[0039] The physical units of the system's architecture include NUMA-based computing units (including processors and associated memory units), multiple high-speed IO controllers (North Bridge), multiple LeagcyIO controllers (South Bridge), independently controllable Power system, FPGA-based partition logic control unit, multiple system management units.

[0040] The usual NUMA architecture is as follows:

[0041] The logic unit includes: processor direct connection bus configuration logic, reset, timing and power control logic, Leagcy-nonLeagcy configuration logic, partition setting logic, processor and partition presence detection lo...

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Abstract

The invention provides a parallel multiprocessor computer design method. The design method comprises the step of partitioning a plurality of processors and IO resources of a computer system on the physical layer to partition one multiprocessor computer system into a plurality of independent multiprocessor systems, wherein the partitioned computer systems can be coupled to one integrated computer system. Therefore, the method can fully partition and allocate computation resources, storage resources and IO resources of the computer according to traffic loads and traffic types, thereby achieving optimized configuration of the system resources. By providing a set of partition control logic and corresponding hardware circuit support, the method can also achieve physical partitioning or coupling of a NUMA (non-uniform memory access) multiprocessor computer system, like a plurality of computer systems completely independent from each other.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a design method for a parallel multiprocessor computer. Background technique [0002] The traditional parallel multiprocessor architecture usually uses processor direct connection bus, storage bus, high-speed IO bus or crossbar switch to connect multiple processors, local memory, and high-speed IO units into a computing unit network, and the entire computing unit network passes through a The group shared bus connects low-speed IO controllers and various external devices, such as SATA, USB, RS232, VGA, etc. Usually we call this kind of low-speed IO controller a LeagcyIO controller, commonly known as a South Bridge chip. The LeagcyIO controller is connected to keyboard and mouse and other input and output devices, connected to LPC and other low-speed buses, connected to EEPROM, FLASH and other configuration memory chips, and storage resources. It has a built-in sequence ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/80
Inventor 林楷智李博乐
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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