Non-volatile memory with P+ single polycrystalline architecture and preparation method for non-volatile memory

Abstract

The invention relates to a non-volatile memory with a P+ single polycrystalline architecture and a preparation method for the non-volatile memory. The non-volatile memory comprises a semiconductor substrate and memory cells, wherein each memory cell comprises a P-channel metal oxide semiconductor (PMOS) access transistor, a control capacitor and a programming capacitor; a gate medium layer is deposited on the surface of the semiconductor substrate; a floating gate electrode is arranged on the gate medium layer, and covers and penetrates through the corresponding gate medium layer above the PMOS access transistor, the control capacitor and the programming capacitor; side protection layers are deposited on two sides of the floating gate electrode; the PMOS access transistor comprises a first N-type area, a P-type source area and a P-type drain area; the control capacitor comprises a second P-type area, a first P-type doping area and a second P-type doping area; and the programming capacitor comprises a third P-type area, a fifth P-type doping area and a sixth P-type doping area. The non-volatile memory is compact in structure and compatible with a complementary metal oxide semiconductor (CMOS) process, the cost of a chip is reduced, and the safety and reliability of the memory are improved.

Description

technical field [0001] The invention relates to a non-volatile memory and a preparation method thereof, in particular to a non-volatile memory with a P+ single polycrystalline structure and a preparation method thereof, belonging to the technical field of integrated circuits. Background technique [0002] For system-on-chip (SoC) applications, it is the integration of many functional blocks into one integrated circuit. The most commonly used SoCs include a microprocessor or microcontroller, static random access memory (SRAM) modules, non-volatile memory, and various special-purpose logic blocks. However, the processes in traditional non-volatile memory, which typically use stacked gate or split gate memory cells, are not compatible with traditional logic processes. [0003] The non-volatile memory (NVM) process is different from the traditional logic process. The combination of non-volatile memory (NVM) technology and traditional logic technology will make the process a mo...

AI Technical Summary

Problems solved by technology

The combination of non-volatile memory (NVM) process and traditional logic process will make the process a more complex and expensive combination; since the typical use of non-volatile memory for SoC applications is in relation to the whole The chip size is small, so this practice is not advisable

At the same time, due to the working principle of the existing non-volatile memory, the written data is easily lost, which affects the reliability of use

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