Method for improving uniformity of poly opening polish nitride chemical-mechanical planarization process

Abstract

The invention provides a method for improving the uniformity of a poly opening polish nitride chemical-mechanical planarization process. Before the silicon oxide layer-targeted chemical-mechanical planarization process, tilt angle ion implantation is conducted for a raised part of a silicon oxide layer and the bonding state of silicon oxide is damaged by using the energy effect of ion implantation; therefore, in the following silicon oxide layer-targeted chemical-mechanical planarization process, the chemical corrosion effect of polishing liquid on the raised part is increased and the removal rate of the material of the raised part is improved, so that height fall existing in the silicon oxide layer does not pass down, the depression of silicon oxide can be avoided, a planar silicon oxide surface is obtained, the possibility of metal residue occurring subsequently can be eliminated and the electric performances and yield of devices can be improved further.

Description

technical field [0001] The invention relates to a process method for manufacturing a semiconductor device, in particular to a method for improving the uniformity of a chemical mechanical planarization process for opening a polycrystalline gate top. Background technique [0002] The successful application of high-K / metal gate engineering on the 45nm technology node makes it an indispensable key modular engineering for technology nodes below 30nm. Currently, only Intel, which adheres to the high-K / gate last route, has achieved success in mass production at the 45nm and 32nm technology nodes. In recent years, Samsung, TSMC, Infineon and other industry giants following the IBM Industry Alliance have also shifted their previous research and development focus from high-K / gate first to gate last. [0003] For the gate last project, the development of the chemical mechanical planarization (CMP) process is considered the most challenging in the industry. In the gate last project, a...

AI Technical Summary

Problems solved by technology

If the conventional silicon oxide CMP technology is adopted, such a large thickness drop cannot be effectively eliminated, and this drop will be transmitted to the end of the silicon oxide CMP as the CMP process progresses, which results in gaps between the polysilicon gates 13. Silicon oxide 11 has depressions

Although there is CMP for silicon nitride 12 afterwards, it is difficult to repair the depression of silicon oxide 11 by CMP in this step, and due to the difference in material selection ratio, the depression of silicon oxide 11 may be further enlarged to form the final silicon oxide depression 14, see figure 2

A large silicon oxide recess 14 will cause a huge obstacle to the metal gate CMP process, and it is easy to form metal residues between the polycrystalline gates 13, thereby causing a device short circuit, see image 3 and Figure 4

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