Compositions and methods for CMP of silicon oxide, silicon nitride, and polysilicon materials

A chemical-mechanical and compositional technology, applied in the field of polishing compositions, which can solve problems such as undiscovered feature combinations

Inactive Publication Date: 2016-03-09
CABOT MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such a combination of features is not typically found in existing CMP compositions or methods

Method used

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  • Compositions and methods for CMP of silicon oxide, silicon nitride, and polysilicon materials
  • Compositions and methods for CMP of silicon oxide, silicon nitride, and polysilicon materials
  • Compositions and methods for CMP of silicon oxide, silicon nitride, and polysilicon materials

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] This example illustrates the effect of various cationic polymers on oxide, nitride and polysilicon removal rates in ceria-based CMP polishing compositions.

[0031] An aqueous polishing slurry having a pH of 4.3 and comprising colloidal ceria (0.4% by weight, primary average particle size of 60 nm) and a cationic polymer was used on a MIRRA polishing device using a DOWIC1010 polishing pad at a platen speed of 100 rpm, a load of 85 rpm. Silicon oxide (TEOS), silicon nitride, and polysilicon blanket wafers were chemically-mechanically polished at a tool speed, a downforce of 3 psi, and a slurry flow rate of 150 mL / min; polishing time: 60 seconds. The polymers and polymer concentrations utilized in the slurries along with the observed removal rates for polishing two wafers each of nitride, oxide and polysilicon (in in units) are shown in Table 1. figure 1 Chemical structure diagrams of selected cationic polymers, including some of the polymers evaluated in this example, ...

Embodiment 2

[0037] This example illustrates the effect of added salt and cationic polymer concentration on oxide, nitride and polysilicon removal rates in a ceria-based CMP polishing composition comprising a methacryloxyalkylammonium polymer. influences.

[0038] An aqueous polishing slurry having a pH of 4.5 and comprising colloidal ceria (0.4% by weight, primary average particle size of 60 nm) and a cationic polymer was used on a MIRRA polishing device using a DOWIC1010 polishing pad at a platen speed of 100 rpm, a load of 85 rpm. Silicon oxide (TEOS), silicon nitride, and polysilicon blanket wafers were chemically-mechanically polished at a tool speed, a downforce of 3 psi, and a slurry flow rate of 150 mL / min; polishing time: 60 seconds. The polymers utilized in the slurries are shown in Table 2. The slurry corresponding to composition 1 had a polymer concentration of 15 ppm, the slurry corresponding to composition 2 had a polymer concentration of 17 ppm, and the slurry corresponding...

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Abstract

The present invention provides a chemical mechanical polishing method for polishing a substrate comprising silicon dioxide, silicon nitride, and polysilicon. The method comprises abrading a surface of the substrate with a CMP composition to remove at least some silicon dioxide, silicon nitride and polysilicon therefrom. The CMP composition comprising a particulate ceria abrasive suspended in an aqueous carrier having a pH of about 3 to 9.5 and containing a cationic polymer; wherein the cationic polymer consists of a quaternary methacryloyloxyalkylammonium polymer.

Description

technical field [0001] The present invention relates to polishing compositions and methods. More specifically, the present invention relates to methods and compositions for polishing substrates containing silicon oxide, silicon nitride and / or polysilicon. Background technique [0002] In memory applications, typical solid-state memory devices (Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable The memory (EEPROM) employs microelectronic circuit elements for each memory bit. For typical non-volatile storage elements such as EEPROM, ie "flash" memory, floating gate field effect transistors are employed as data storage devices. These devices hold charges on the gates of field effect transistors to store memory bits and have limited reprogrammability. Also, they are slow to program. [0003] During semiconductor and memory device fabrication, various layers of materia...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/304
CPCB24B1/00C09G1/02C09K3/1463H01L21/31053H01L21/3212C09G1/00C09G1/04C09K13/06H01L21/30625
Inventor D.丹加K.莫根博格W.沃德D.马特加
Owner CABOT MICROELECTRONICS CORP
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