Semiconductor structure with low resistance substrate and low power loss

Abstract

The invention provides a semiconductor structure with a low resistance substrate and low power loss. The semiconductor structure comprises a semiconductor unit, a first conductive structure, a first conductive material and a second conductive structure, wherein the semiconductor unit is provided with a substrate, and the substrate is positioned at one side of the semiconductor unit and is provided with at least one hole; the first conductive material is positioned in the hole in a filling-in or underfilling way, and the first conductive structure is positioned on one surface of the side of the semiconductor unit; and the second conductive structure is positioned on the surface of the other side of the semiconductor unit different from the semiconductor substrate. The semiconductor structure can effectively reduce the resistance of the substrate, and further reduce the power loss during the breakover on the semiconductor structure, and also has a longer service life. In addition, without adding additional equipment, the advantages of the current packaging factory capacity can be continuously utilized, so that the power loss and potential die crack risks are further reduced.

Description

technical field [0001] The invention relates to a semiconductor structure, in particular to a semiconductor structure with low power loss. Background technique [0002] For the application of power metal oxide semiconductors, the most important thing is its electrical specifications and heat dissipation capabilities, and the parameter that most affects it is the on-resistance Rds(ON) of the drain and source. Generally speaking, Rds(ON) roughly includes the on-resistance of the chip itself and the resistance formed during packaging, so how to reduce the resistance of the two has become an important issue. General traditional vertical power metal oxide semiconductors, such as figure 1 As shown, the thickness of the substrate 101 accounts for more than 90% of the overall chip, but the ratio of the resistance of the substrate to the overall chip resistance will increase as the operating voltage of the power metal oxide semiconductor decreases, for example, 600 volts The resist...

AI Technical Summary

Problems solved by technology

The traditional method of reducing the resistance of the substrate uses chip thinning technology to mechanically thin the power metal oxide semiconductor chip from about 300 microns (μm) to about 50 μm. figure 2 As shown in the vertical power metal oxide semiconductor structure with a thinned substrate, the thinned chip is then subjected to subsequent semiconductor packaging processes. However, such a thin chip will greatly increase the probability of fragmentation during the subsequent process and transportation process. In order to protect such a thin chip, in each process, it is necessary to add additional processing procedures and equipment to protect the chip from cracking, resulting in a significant increase in cost

Furthermore, in the packaging and bonding process, the chip must withstand instantaneous stress. Such a thin chip is prone to the potential risk of micro-cracks, resulting in a significant reduction in the usable life of the product.

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