Method and system for simulating on-chip power supply network

A technology of power supply network and simulation method, which is applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., and can solve the problems of not being able to meet the actual design requirements well, not being able to conduct large-scale power supply network analysis, and having a large design scale

Active Publication Date: 2012-09-12
TSINGHUA UNIV
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Problems solved by technology

The traditional method is to use a SPICE simulator, which uses LU decomposition technology to directly solve the linear system equations. For the current power supply network simulation with a scale of millions of nodes, the memory consumption is extremely huge and cannot be solved. Analyze large-scale power supply networks
The coefficient matrix of the matrix equation formalized by the power supply network system has good properties such as sparse, symmetric, positive definite, and diagonally dominant. At present, the existing power supply network analysis methods include the multi-grid method, the preconditioned conjugate gradient method, and the hierarchical method. and random walk, etc., but due to the large design scale, the above methods still cannot meet the actual design requirements well

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  • Method and system for simulating on-chip power supply network

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Embodiment Construction

[0065] The invention provides an on-chip power supply network simulation system with linear complexity, which includes an efficient SPICE netlist parser, an efficient circuit builder, and a fast linear system solver. Using this simulation system, the power supply network in SPICE netlist format can be quickly and accurately analyzed for static voltage drop, and it has good convergence stability. The power supply network simulation system first reads the netlist in SPICE format, stores the electrical components and node information in the power supply network into the data structure, and then builds the power supply network into a simulation matrix and the right-hand current vector. The conjugate gradient algorithm with the grid as a preprocessing sub-process solves the node voltage vector of the power supply network and outputs it.

[0066] The present invention will be described in detail below with reference to the accompanying drawings.

[0067] The on-chip power supply ne...

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Abstract

The invention discloses a method and a system for simulating an on-chip power supply network. The method comprises the following steps: step 1, reading in an SPICE (simulation program with integrated circuit emphasis) netlist; step 2, establishing a power supply network topological diagram; step 3, establishing a matrix equation Ax=b, wherein A is an electric conduction matrix of n*n, x is a knot voltage vector to be solved of the power supply network, b is current and n is number of thin grid points; and step 4, solving a roughened operator by utilizing a grid point dual polymerization algorithm, and solving the matrix equation by utilizing the roughened operator. The invention provides a static simulation project for the power supply network, and the simulation project is more stable and efficient, and less in occupied memory, and has linear complexity, under the condition that the solving precision appointed by the user is satisfied, the project can achieve an analysis of a knot voltage drop of the power supply network in an appointed form of the SPICE net list in a way that the operation time is reduced and the memory is used as little as possible.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an on-chip power supply network simulation method and system. Background technique [0002] In VLSI, an important prerequisite for the normal operation of each component is that it can obtain a normal power supply voltage. In fact, with the continuous reduction of the size of the integrated circuit process, the network impedance of the integrated circuit power supply system under the planar process design is getting larger and larger, and the voltage drop on the metal traces of the power supply system has become non-negligible, that is, the element The actual supply voltage obtained on the device will be less than the external supply voltage. If the voltage drop on the power supply network is too large, the power supply voltage obtained by the components may be too low, resulting in an increase in the delay of the components, affecting the performance of the chip, and ev...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 蔡懿慈周强杨建磊李佐渭
Owner TSINGHUA UNIV
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