Ultra-high-current high-frequency FRD chip and manufacturing method thereof
A FRD and diode technology, applied in the field of power semiconductor devices, can solve the problems of large forward voltage, little consideration of the influence of longitudinal diffusion parameters and distribution, large power consumption, etc., achieves high avalanche characteristics, is conducive to soft recovery, quick recovery effect
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Embodiment 1
[0039] Such as figure 1 , figure 2 As shown, the manufacturing method of the ultra-high-current high-frequency FRD diode chip is as follows:
[0040] 1. Wafer preparation
[0041] Use an N-type silicon single wafer with a thickness of 170 μm, a uniform cross-sectional resistivity, and a cross-sectional resistance of 3Ω / □~5Ω / □ as the N-type substrate 2, △ρn / ρn (resistivity change / average resistivity)=7% 1. The width of the base region of the silicon wafer is 1.1 times the width of the space charge region to ensure a non-through structure; and then the silicon wafer is cleaned.
[0042] 2. N+ diffusion
[0043] An N+ region 3 is fabricated on an N-type substrate 2, the junction depth of the N+ region 3 is 20 μm, and the diffusion resistance R sp+ =1.6Ω / □.
[0044] 3. N++ and P++ Diffusion
[0045] Diffusion of N++ and P++ is carried out on the front and back of the N-type substrate 2 at the same time to make N++ region 4 and P++ region 1, wherein the junction depth of N++...
Embodiment 2
[0051] Such as figure 1 , figure 2 As shown, the manufacturing method of the ultra-high-current high-frequency FRD diode chip is as follows:
[0052] 1 Wafer preparation
[0053] Use an N-type silicon single wafer with a thickness of 190 μm, a uniform cross-sectional resistivity, and a cross-sectional resistance of 5Ω / □ to 8Ω / □ as the N-type substrate 2, △ρn / ρn=10%, and the width of the base area of the silicon wafer is 1.12 times the space The width of the charge region ensures a non-through structure; then cleans the silicon wafer.
[0054] 2. N+ diffusion
[0055] An N+ region 3 is fabricated on an N-type substrate 2, the junction depth of the N+ region 3 is 24 μm, and the diffusion resistance R sp+ =2Ω / □;
[0056] 3. Full diffusion of N++ and P++
[0057] Diffusion of N++ and P++ is carried out simultaneously on the front and back of the N-type substrate 2 to form N++ region 4 and P++ region 1, wherein the junction depth of N++ region 4 is 25 μm, and the diffusion...
Embodiment 3
[0063] 1 Wafer preparation
[0064] Use an N-type silicon single wafer with a thickness of 208 μm, a uniform cross-sectional resistivity, and a cross-sectional resistance of 5Ω / □ to 15Ω / □ as the N-type substrate 2, △ρn / ρn=15%, and the width of the base area of the silicon wafer is 1.15 times the space The width of the charge region ensures a non-through structure; then cleans the silicon wafer.
[0065] 2. N+ diffusion
[0066] An N+ region 3 is fabricated on an N-type substrate 2, the junction depth of the N+ region 3 is 30 μm, and the diffusion resistance R sp+ =2.4Ω / □.
[0067] 3. N++ and P++ Diffusion
[0068] Diffusion of N++ and P++ is carried out simultaneously on the front and back of the N-type substrate 2 to form N++ region 4 and P++ region 1, wherein the junction depth of N++ region 4 is 28 μm, and the diffusion resistance R sp+ =0.5Ω / □; the junction depth of P++ region 1 is 90μm, and the diffusion resistance R sp+ =2.5Ω / □.
[0069] 4. Platinum expansion at ...
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