Ultra-high-current high-frequency FRD chip and manufacturing method thereof
A manufacturing method and FRD technology, which are applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of large forward voltage, little consideration of the influence of longitudinal diffusion parameters and distribution, and large power consumption. High avalanche characteristics, favorable for soft recovery and fast recovery
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Embodiment 1
[0039] Such as figure 1 , figure 2 As shown, the manufacturing method of the ultra-high-current high-frequency FRD diode chip is as follows:
[0040] 1. Wafer preparation
[0041] Use an N-type silicon single wafer with a thickness of 170 μm and a uniform cross-sectional resistivity of 3Ω / □ to 5Ω / □ as the N-type substrate 2, △ρn / ρn (resistivity change / average resistivity)=7%, silicon The width of the base region is 1.1 times the width of the space charge region to ensure a non-through structure; then the silicon wafer is cleaned.
[0042] 2. N + diffusion
[0043] Fabricate N on N-type substrate 2 + Region 3, the junction depth of the N+ region 3 is 20 μm, and the diffusion resistance R sp+ =1.6Ω / □.
[0044] 3. N ++ and P ++ diffusion
[0045] Perform N on the front and back of the N-type substrate 2 simultaneously. ++ and P ++ Diffuse, make N ++ Zone 4 and P ++ District 1, where N ++ The junction depth of region 4 is 20μm, and the diffusion resistance R sp+ =...
Embodiment 2
[0051] Such as figure 1 , figure 2 As shown, the manufacturing method of the ultra-high-current high-frequency FRD diode chip is as follows:
[0052] 1 Wafer preparation
[0053] Use an N-type silicon single wafer with a thickness of 190 μm and a uniform cross-sectional resistivity of 5Ω / □~8Ω / □ as the N-type substrate 2, △ρn / ρn=10%, and the width of the base area of the silicon wafer is 1.12 times the space charge area Width, ensure non-through structure; then silicon wafer cleaning.
[0054] 2. N + diffusion
[0055] Fabricate N on N-type substrate 2 + District 3, the N + Zone 3 junction depth 24μm, diffusion resistance R sp+ =2Ω / □;
[0056] 3. N ++ and P ++ total diffusion
[0057] Perform N on the front and back of the N-type substrate 2 simultaneously. ++ and P ++ Diffusion, forming N ++ Zone 4 and P ++ District 1, where N ++ The junction depth of region 4 is 25μm, and the diffusion resistance R sp+ =0.4Ω / □;P ++ The junction depth of region 1 is 85μm, ...
Embodiment 3
[0063] 1 Wafer preparation
[0064] Use an N-type silicon single wafer with a thickness of 208 μm and a uniform cross-sectional resistivity of 5Ω / □ to 15Ω / □ as the N-type substrate 2, △ρn / ρn=15%, and the width of the base area of the silicon wafer is 1.15 times the space charge area Width, ensure non-through structure; then silicon wafer cleaning.
[0065] 2. N + diffusion
[0066] Fabricate N on N-type substrate 2 + District 3, the N + Zone 3 junction depth 30μm, diffusion resistance R sp+ =2.4Ω / □.
[0067] 3. N ++ and P ++ diffusion
[0068] Perform N on the front and back of the N-type substrate 2 simultaneously. ++ and P ++ Diffusion, forming N ++ Zone 4 and P ++ District 1, where N ++ The junction depth of region 4 is 28μm, and the diffusion resistance R sp+ =0.5Ω / □;P ++ The junction depth of region 1 is 90μm, and the diffusion resistance R sp+ =2.5Ω / □.
[0069] 4. Platinum expansion at low temperature
[0070] After simultaneously expanding boron and ...
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