Mold array process method for covering side edge of substrate

An array processing and substrate technology, which is applied in the field of packaging manufacturing, can solve problems such as the protection of the sealing body 130, adverse effects, and the inability of the side 116 to achieve the effect of avoiding exposure and improving durability

Active Publication Date: 2012-10-03
WALTON ADVANCED ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the substrate unit 113 is cut according to the cutting lines 114, the sealing body 130 and the substrate strip 110 will be cut through at the same time, so that the substrate unit 113 has an exposed side edge 116 that is aligned with the cut side of the sealing body 130, That is, the side 116 of the substrate unit 113 cannot be protected by the sealing body 130
Therefore, after singulation

Method used

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  • Mold array process method for covering side edge of substrate
  • Mold array process method for covering side edge of substrate
  • Mold array process method for covering side edge of substrate

Examples

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no. 1 Embodiment

[0034] According to the first embodiment of the present invention, a molding array processing method covering the side of the substrate is exemplified in image 3A schematic cross-sectional view showing the structure of the semiconductor package made by it, Figure 4A to Figure 4F The cross-sectional schematic diagram of the components in each step and Figure 5 A partial top view of its substrate strip is shown. The details are as follows.

[0035] First, see Figure 4A and Figure 5 As shown, a substrate bar 210 is provided, which has more than four substrate units 212, which are integral connection parts inside the substrate bar 210 during the process and are reserved substrate parts in the semiconductor package structure after the process is manufactured, for Carrying and electrically connecting the chip. The substrate units 212 are arranged in a matrix 211 of N times M. Such as Figure 5 As shown, N is 2, M is 3, and a plurality of substrate units form a 2×3 matrix...

no. 2 Embodiment

[0042] According to the second embodiment of the present invention, another molding array processing method for covering the side of the substrate is exemplified in Figure 6A to Figure 6H The cross-sectional schematic diagrams of components in each step are used to illustrate that the present invention is applicable to different packaging types, wherein the main components that are the same as those in the first embodiment are marked with the same symbols and will not be described in detail.

[0043] see Figure 6A As shown, a substrate strip 210 is provided having more than four substrate units 212 arranged in an N by M matrix 211 . In this embodiment, in addition to the internal circuit structure, the substrate strip 210 may have more than two internal leads 319 exposed in the central slots 215 of the substrate units 212 . These inner leads 319 can be the extensions of the inner metal circuit layer of the substrate strip 210 or additional suspended inner leads (leads) from...

no. 3 Embodiment

[0049] According to the third embodiment of the present invention, another molding array processing method for covering the side of the substrate is exemplified in Figure 7A to Figure 7G The cross-sectional schematic diagrams of components in each step are used to illustrate that the pre-cut holes need not be formed in the step of providing substrate strips, and the main components that are the same as those in the first embodiment are marked with the same symbols and will not be described in detail.

[0050] see Figure 7A As shown, a substrate strip 210 is provided having more than four substrate units 212 arranged in an N by M matrix 211 . see Figure 7B As shown, more than two chips 220 are disposed on the substrate units 212 , and these chips 220 are electrically connected to the substrate units 212 . see Figure 7C As shown, a dicing tape 470 can be pasted on the lower surface 217 of the substrate strip 210 to carry the substrate strip 210 and be used for subsequent ...

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Abstract

The invention discloses a mold array process method for coating the side edge of a substrate. More than four substrate units of a substrate strip are arrayed into a matrix. Cutting channels are respectively formed between adjacent substrate units and on the periphery of the matrix; and precutting slotted holes with the widths greater than those of the corresponding cutting channels are formed along the cutting channels. A sealing colloid is formed on the substrate strip through mold sealing to continuously cover the substrate units and the cutting channels; and the sealing colloid is enabled to be filled into the precutting slotted holes to cover the side edges of the substrate units. Through monomer separating, the substrate units form semiconductor packing structures, and the side edges of the cut substrate units are still covered by the sealing colloid. Therefore, the problem that the electroplated lines of the substrate units in the mold array process are exposed is solved, and the wet resistance of the semiconductor packing structures is further improved.

Description

technical field [0001] The present invention relates to the packaging and manufacturing technology of semiconductor devices, in particular to a molding array processing method for covering the sides of substrates. Background technique [0002] Traditionally, based on cost considerations and mass production requirements in semiconductor packaging technology, the Mold Array Process (MAP) process is commonly used. A substrate strip (Substrate Strip) is used as a carrier for multiple chips. The substrate strip contains more than four substrate units arranged in a matrix. After semiconductor packaging operations such as setting chips and electrical connections, a mold with an area larger than the matrix is ​​formed. The encapsulant continuously covers the substrate unit and the dicing lines between the substrate units, and then singulates along the dicing line to obtain more than four semiconductor package structures. [0003] figure 1 It is a semiconductor package structure in...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/56
CPCH01L24/97H01L2924/15311H01L2224/4824H01L2224/97H01L2224/73265H01L2224/48227H01L2224/73215H01L2224/32225H01L2224/50H01L24/73H01L2924/181
Inventor 李国源陈永祥邱文俊
Owner WALTON ADVANCED ENG INC
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