Test data compression method capable of rapidly searching irrational number

Abstract

The invention discloses a test data compression method capable of rapidly searching an irrational number. The test data compression method comprises the following steps of: generating a determined complete test set T and marking the number of test vectors of the complete test set to be N; marking cascading of all test vectors to be S and the length of cascading to be w; calculating the length of runs and ending till reaching an irrelevant position and converting the length information of runs into a decimal x for representing; searching the irrational number and expanding the irrational number to a decimal, wherein the front p items of the decimal are just equal to x, and only integers, namely m, n, l, k and p are stored in the compression process. The test data compression method disclosed by the invention has the advantages that methods of first searching the irrational number and then carrying out bit-by-bit comparison are adopted in the irrelevant bit filling process, and thus the selectivity of the irrational number and the probability of searching the irrational number are increased; and according to the test data compression method, an interval bisection method is adopted in the irrational number searching process, and therefore the operating time can be prolonged according to a logarithm rule.

Description

technical field [0001] The invention relates to a method for compressing test data in a built-out self-test (Built-Out Self-Test, BOST) method for a system chip (System-on-a-Chip, SoC), in particular to a test for quickly finding irrational numbers Data compression method. Background technique [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in one chip, and can integrate pre-designed and verified IP, such as memory, microprocessor, DSP, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system-on-chip or system-on-a-chip. SoC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market, but the testing of SoC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, ...

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. Automatic test equipment (ATE) is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more IP integrated in the SoC, the greater the amount of test data required

However, there are two problems in this invention: (1) before searching for irrational numbers, all irrelevant bits are filled, which reduces the flexibility of the algorithm and the probability of finding irrational numbers; (2) for searching for irrational numbers, the It is a method of direct operation on decimals, which requires a large amount of calculation and takes a long time to run

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