Method for manufacturing power transistor

Abstract

The invention discloses a method for manufacturing a power transistor. By the method, insulating dielectric layers formed on the top of grid polycrystalline silicon and side-wall dielectric layers formed on side surfaces of the insulating dielectric layers are used as etching hard masks of a pressure bearing region, the quantity of masks required by a front-surface process is reduced, and the density of a transistor in a chip can be increased. A P-type polycrystalline silicon layer is planted into a P-type well region and is subjected to short circuit with a source electrode via metal contact, cavity flows of the P-type well region flow out advantageously, and accumulated cavities are reduced, so that latch-up resistance of a device is improved. The method is favorable for obtaining a power device with low conducting resistance, low saturation voltage drop and high current driving capacity.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a power transistor manufacturing method. Background technique [0002] In the application of power and high-voltage devices, it is hoped that the on-resistance of the transistor will be smaller, the saturation voltage drop will be lower, and the current driving capability will be greater. How to integrate more devices within a certain chip area is particularly important. However, the alignment deviation between different masks makes the device size unable to be reduced according to the demand, and the more precise photolithography technology makes the manufacturing cost expensive, which is not conducive to mass production. In addition, when the hole current in the well region reaches a certain level, the potential of the well region will be raised, and the source-well junction barrier will be lowered, causing the parasitic bipolar transistor to be...

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Problems solved by technology

However, the alignment deviation between different masks prevents the size of the device from being reduced according to demand, and the more precise photolithography technology makes the manufacturing cost expensive, which is not conducive to mass production.

In addition, when the hole current in the well region reaches a certain level, the potential of the well region will be raised, and the source-well junction barrier will be lowered, causing the parasitic bipolar transistor to be turned on. At this time, the gate cannot control the current switch, and a latch occurs effect

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