Method for processing semiconductor device and semiconductor device

Abstract

The invention relates to the technical field of a semiconductor device, and in particular relates to a method for processing the semiconductor device and the semiconductor device. The method comprises the steps of: etching an epitaxial layer to form a channel after forming an initial oxide layer on the upper surface of the epitaxial layer of a substrate; carrying out polycrystalline silicon growth on the epitaxial layer after forming a grid oxide layer on the inner surface of the channel; after reversely etching the polycrystalline silicon, achieving that the top plane of the polycrystalline silicon in the channel is lower than that of the channel; depositing a medium layer, wherein the medium layer covering the surface of the initial oxide layer is different from that covering the surface of the polycrystalline silicon in the channel in height in vertical direction; and after removing the medium layers and the initial oxide layer on the surface of the epitaxial layer, carrying out metal layer growth. According to the method for processing the semiconductor device and the semiconductor device provided by the embodiment of the invention, as source region photoetching and contact hole photoetching processes are cancelled, the cost is further saved. The distance between adjacent channels is reduced, and the size of cell is shortened, so that the current conducting capacity of a chip is improved.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor devices, in particular to a method for processing a semiconductor device and the semiconductor device. Background technique [0002] The cell density of the vertical double diffused metal oxide semiconductor transistor VDMOS device most directly affects the total chip area of ​​the VDMOS device, the ability of the chip to conduct current per unit area, and has the greatest relationship with the chip manufacturing cost. [0003] At present, in the manufacturing process of trench-type VDMOS devices, the fabrication of SRC (source) region and CONT (contact hole) requires the corresponding photolithography pattern to be made between the trenches. Since the photolithography pattern itself has a certain set Accuracy deviation, the photoresist pattern itself has a certain size, so the distance between the trenches cannot be too close, so that the size of the cell of the semiconductor device...

AI Technical Summary

Problems solved by technology

[0006] In summary, since a certain distance must be kept between the two trenches, the size of the cell is larger, the ability of the chip to conduct current is poor, and the production cost is high.

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