Method for producing zero layer photoetching marking of high-voltage device without barrier layers

Abstract

The invention discloses a method for producing zero layer photoetching marking of a high-voltage device without barrier layers. The method for producing the zero layer photoetching marking of the high-voltage device without the barrier layers comprises the following steps: (1) etching a zero layer lithography marking groove, (2) depositing a layer of medium layer and removing medium layers of regions outside the zero layer lithography marking groove, (3) etching a deep groove, (4) selectively growing an epitaxial layer on a silicon substrate, (5) removing anti-configuration epitaxial materials deposited on the silicon substrate in the epitaxial growth process of epitaxial layer, (6) etching away a medium layer inside the zero layer lithography marking groove by the adoption of the method of wet etching and leaving a zero layer lithography marking graph. Through the method for producing the zero layer photoetching marking of the high-voltage device without the barrier layers, lithography markings which are easy to recognize can be formed on the high-voltage device without the barrier layers, and therefore a follow-up film layer can be directed at conveniently, smooth of technological process can be guaranteed, and good yield of a product is improved.

Description

technical field [0001] The invention relates to a semiconductor process method, in particular to a method for making a zero-layer photolithography mark of a high-voltage-resistant device without a barrier layer. Background technique [0002] In today's semiconductor power applications, a new type of semiconductor device has emerged that can both increase the breakdown voltage and reduce the resistance in the on-state. It has alternately arranged PN column layers, which function as a super junction as a drift layer. [0003] The method of etching and filling deep trenches in the manufacturing process of super junction MOS transistors is to grow a layer of n-type epitaxial layer (single crystal silicon) on the n+ type silicon substrate, and then deposit a layer or Several layers of oxide film or nitride film, etch the deep trench, and fill the deep trench with p-type single crystal silicon for selective epitaxy, and finally use chemical mechanical polishing (CMP) process to p...

AI Technical Summary

Problems solved by technology

However, since the high-voltage device is directly etched and patterned on the silicon substrate, the deep trench is filled with epitaxial technology. Due to the existence of no barrier layer in the zero-layer cursor pattern, it will lead to a problem in filling the deep trench. At the same time as the trench, the epitaxial layer will also be filled in the pattern of the zero-layer lithography mark, and the deep trench filling and the silicon substrate are both single crystals. In the subsequent chemical mechanical polishing process, there is no high selectivity. If the gap is too small, the photolithographic mark cannot be recognized, which makes it impossible to use the zero-layer pattern in the subsequent process, which brings difficulties to the alignment of subsequent film layers, affects the smooth process flow, and affects the yield of the product.

[0007] like figure 1 As shown, the zero-layer lithography mark is filled by the epitaxial layer (EPI) and cannot be read

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