A kind of preparation method of gaasoi structure and Ⅲ-ⅴoi structure

Abstract

The invention provides a preparation method of a GaAsOI (GaAs On Insulator) structure and an III-VOI (III-V On Insulator) structure. The preparation method comprises the steps of: forming a semiconductor substrate and a GaAs layer structure first through the epitaxy technology and ion implantation technique, wherein the semiconductor substrate has an H ion or / and He ion implantation layer and the semiconductor substrate is a Ge, Ge / Si, Ge / GeSi / Si or GOI (Germanium On Insulator) substrate; forming a first SiO2 layer on the surface of the GaAs layer; bonding a Si substrate with a second SiO2 layer on the surface, carrying out first anneal reinforced bonding and carrying out second annealing to peel the implantation layer; removing the residual semiconductor substrate on the surface of the GaAs layer by XeF2 gaseous corrosion to obtain the GaAsOI structure; and obtaining a high quality III-VOI structure by adopting similar schemes. According to the invention, the high quality GaAs layer and III-VOI semiconductor layer can be obtained by means of molecular beam epitaxy or ultrahigh vacuum chemical vapor deposition. The residual semiconductor substrate which is intelligently peeled can be effectively removed, while the integrity of the GaAs layer can be maintained through a method of high selectivity gas corrosion, so that the high quality GaAsOI or III-VOI can be effectively prepared.

Description

technical field [0001] The invention relates to a method for preparing a semiconductor material, in particular to a method for preparing a GaAsOI structure and a III-VOI structure. Background technique [0002] SOI (Silicon-On-Insulator, silicon on insulating substrate) technology introduces a buried oxide layer between the top silicon and the back substrate. By forming a semiconductor thin film on an insulator, the SOI material has the incomparable advantages of bulk silicon: it can realize the dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits; The integrated circuit also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect, and is especially suitable for low-voltage and low-power circuits. Therefore, it can be said that SOI will likely become a deep submicron low-voltage , The mainstream technology of low...

AI Technical Summary

Problems solved by technology

[0003] However, according to the planning of the International Semiconductor Industry Development Blueprint (ITRS2009), integrated circuits have gradually developed from the era of microelectronics to the era of micro-nanoelectronics. its physical limit

Below the 32nm technology node, especially below 22nm, the structure and materials of transistors will face more challenges

However, when GaAsOI and most other Ⅲ-VOI materials are prepared by the Smart Cut process, the extensiveness of this method is limited due to the high ion implantation temperature required.

Especially when using the Smart Cut process to strip GaAs, the ion implantation temperature in GaAs is required to be above 150°C, even 300°C, and the implantation dose of H ions or / and He ions is required to be as high as ~10 17 Order of magnitude or more, that is, it needs to be injected at a higher temperature for a longer time to achieve peeling, which greatly limits its wide use

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