A method for making outer layer graphics of partially gold-plated printed boards
A technology of outer layer pattern and production method, which is applied in the direction of printed circuit manufacturing, reinforcement of conductive pattern, printed circuit, etc.
Active Publication Date: 2015-08-12
JIANGNAN INST OF COMPUTING TECH
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Problems solved by technology
[0006] The technical problem to be solved by the present invention is to provide a method for making the outer layer pattern of a partially gold-plated printed board in view of the above-mentioned defects in the prior art, so as to avoid the problems of many lead-in process lines and difficult process line stripping in the subsequent partial gold-plated surface treatment
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[0023] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below with reference to specific embodiments and drawings.
[0024] figure 1 It schematically shows a flow chart of a method for manufacturing an outer layer pattern of a partially gold-plated printed board according to a preferred embodiment of the present invention.
[0025] Specifically, such as figure 1 As shown, the method for manufacturing the outer layer pattern of a partially gold-plated printed board according to a preferred embodiment of the present invention includes:
[0026] The first step S1: the printed board is conventionally plated and thickened and ground and flattened, so that the outer layer of etching base copper 2 meets the design requirements of the conductor thickness of the printed board, and the outer layer of etching base copper 2 is located outside the printed board Layer dielectric layer 1 surface,...
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The invention provides a making method of outer layer patterns of a local gold-plating printed plate. A printed plate is conducted to conventional plate planting and thickening and is ground to be smooth, so that outer layer etched base copper is in accordance with the requirements on the thickness of a printed plate finished conductor. A gold-plating resistant dry film is bonded on the printed plate, dry film window cutting is performed in a gold-plating pattern area, and then electrogilding treatment and stripping are performed. Tin-plating resistant dry film is bonded on the printed plate, dry film window cutting is performed in an area corresponding to pattern design other than the gold-plating area, patterns exposed after window cutting are conducted to tin plating, so as to be served as a tin plate of an alkaline etching resistant protective layer, and stripping is performed after tin plating. The gold-plating layer and the tin layer are both served as etching resistant layers, and outer layer conductor patterns are prepared through an alkaline etching technology. Peelable blue gel is screen-printed on the outer layer gold-plating conductor patterns and is cured, so that the gold-plating area is protected, and then the tin layer is conducted to tin stripping treatment. Solder resist is prepared and other surface treatment is performed.
Description
Technical field [0001] The present invention relates to the field of printed circuit board manufacturing, and more specifically, the present invention relates to a method for manufacturing the outer layer pattern of a partially gold-plated printed board. Background technique [0002] In order to meet the requirements of different functions on the surface of printed boards, more and more printed boards require targeted two or more combined surface treatments. In addition, due to the low contact resistance, oxidation resistance, and high surface flatness of the gold-plated surface layer, the hard gold has excellent wear resistance and the soft gold has good solderability, so the surface treatment of gold-plated (including soft gold and hard gold) has been marked Wide attention and application in the board industry. But at the same time, the gold-plating process is costly, and the gold-plated small-sized pads are prone to defects of gold layer embrittlement after soldering. [0003]...
Claims
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IPC IPC(8): H05K3/18H05K3/24
Inventor 方庆玲吴小龙吴梅珠徐杰栋刘秋华胡广群梁少文曹刚
Owner JIANGNAN INST OF COMPUTING TECH