A method for on-chip and off-chip allocation of embedded memory data

Abstract

The invention relates to an on-chip and off-chip distribution method for embedded memory data. An on-chip memory serving as the key part of an embedded system directly affects the integral performance of the system. The on-chip and off-chip distribution method firstly proposes that a TCG (trusted computing group) model is used as a new standard for measuring a data object to cause Cache missing, and majority of key factors, such as the data object size, the life cycle, the access times, the time locality and the space locality, are comprehensively considered; then, an SPM(scratch pad memory) / Cache data distribution method is proposed to distribute a data object, which most likely generates confliction (big TCG value), to an SPM; and finally, a fixed Cache data layout method is proposed to map the data object with the big TCG value to different Cache groups to avoid confliction. According to the method disclosed by the invention, on-chip memory hardware and software operated on the on-chip memory hardware are better matched, and time for a program to access a memory system is shortened so as to improve the integral performance of the system.

Description

technical field [0001] The invention belongs to the technical field of embedded memory. In particular, it relates to a method for on-chip and off-chip allocation of embedded memory data. The present invention can achieve optimal performance on specific memory configuration for specific applications, and is especially suitable for performance optimization of multimedia application programs on the hybrid memory structure of scratch pad memory / cache cache. Background technique [0002] Due to differences in manufacturing process and circuit logic structure, the speed of processor execution components has always been higher than the read and write speed of memory, and with the development of semiconductor process technology, the performance difference caused by this speed gap is gradually increasing. An important technology to solve the speed mismatch between the processor and the external memory is that the storage system adopts a layered design and integrates a small but fast...

AI Technical Summary

Problems solved by technology

However, the small capacity and specificity of SPM make how to effectively use on-chip memory resources a key issue in embedded system design

[0004] Existing software data storage optimization research mainly focuses on how to increase the Cache command rate, or how to increase the number of SPM accesses, lack of research on data memory access optimization using the Cache and SPM hybrid on-chip memory structure

Images