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Single-chip integrated circuit with capacitive isolation

An integrated circuit, capacitive technology, applied in the direction of circuits, capacitors, electrical components, etc., can solve problems such as can not be easily isolated

Inactive Publication Date: 2013-07-31
SILANNA GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] However, these techniques are currently limited to data rates of ~150Mbps
Due to the emergence of new high-speed signaling standards (including USB2480Mbps, USB3, Firewire, and Gigabit Ethernet), so far, it cannot be easily and effectively isolated

Method used

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  • Single-chip integrated circuit with capacitive isolation
  • Single-chip integrated circuit with capacitive isolation
  • Single-chip integrated circuit with capacitive isolation

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0100] Example 1: Lateral capacitor on SOS substrate:

[0101] Dielectric strength between metal and passivation oxide: 1000V / μm

[0102] Sealant dielectric strength: 15V / μm

[0103] Sapphire dielectric strength: 50V / μm

[0104] Air: 2V / μm

[0105] Top passivation thickness Tpass: 1μm

[0106] If an isolation tolerance of 5kV is required, then image 3 The dimensions shown in are selected to have the following minimum values:

[0107] (I) Wsub=100μm (through the active layer 214Si-Si breakdown of the sapphire substrate 216);

[0108] (Ii) Tsub=50μm (through the substrate 216 down to the conductive layer or the active layer 214Si-Si breakdown of the sealant 236);

[0109] (Iii) Wgap=5μm (transverse breakdown through the dielectric between the capacitor plates);

[0110] (Iv) Tbot=2.5μm (the breakdown between the capacitor plates down to the substrate 216);

[0111] (V) Ttop=2.5μm (up to the breakdown between the capacitor plates in the sealant 236);

[0112] (Vi) Wcap1=200μm (breakdown between...

example 2

[0115] Example 2: Lateral capacitor on a buried oxide SOI substrate:

[0116] The dielectric strength of the buried oxide (BOX) on the SOI chip is much higher than that of sapphire; in this example, the strength is 1000V / μm.

[0117] For 5kV isolation, the dimensions given in the above SOS example apply, except for the following:

[0118] (I) Wsub=5μm; and

[0119] (Ii) Tsub=2.5μm.

[0120] Seal ring configuration

[0121] Sealing rings (also called'chip seals' in this technology) are used around integrated circuits to protect circuits on the chip from contaminants diffused from the sealant material, and also prevent cracks from propagating into the chip. Generally, the sealing ring includes a plurality of continuous metal, polysilicon, and active silicon rings, and is electrically grounded, the continuous ring is around the circuit core and as close as possible to the core to reduce the overall chip area. However, the inventors have determined that the seal ring represents a breakdow...

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PUM

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Abstract

An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and / or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.

Description

Technical field [0001] The present invention relates to an integrated circuit, in particular to a monolithic or monolithic integrated circuit with capacitive isolation and a method for manufacturing an integrated circuit. Background technique [0002] For most applications, the transmission of signals across the electrical isolation barrier is important. Applications include the following: [0003] Medical equipment connected to the mains power supply (for the safety of patients); [0004] Communication links through cables between devices connected to the mains power supply (in order to avoid ground loops), such as USB, FireWire, Ethernet, etc.; [0005] Isolate telecommunications equipment in telephone lines (used for lightning protection); [0006] Mains power data network (used for mains power isolation); [0007] Accurate audio, detection and data collection (used to suppress noise pickup); [0008] Industrial detection and control (for isolation of various power domains); [0009] A...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/00H01L23/52H10N97/00
CPCH01L23/5223H01L27/0255H01L2224/48091H01L2224/73265H01L2224/32245H01L2224/49171H01L23/48H01L2224/48247H01L2924/00014H01L2924/00H01L2924/181H01L2924/00012H01L23/5222H01L23/60H01L27/0629H01L27/0207H01L27/0248H01L28/40H01L27/0292H01L29/0607
Inventor 亚肖德汉·维贾伊·莫盖安德鲁·特里安德鲁·詹姆斯·里德史蒂文·格兰特·杜瓦尔
Owner SILANNA GRP