Preparation method of p-layer silicon epitaxial wafer on p++ substrate

Abstract

The invention discloses a preparation method of a P-layer silicon epitaxial wafer on a P++ substrate, and belongs to the technical field of silicon epitaxial wafers. The preparation method comprises the steps as follows: (1) selecting a P+<111> / Boron single-face polished section; (2) performing HCl polishing; (3) sweeping; and (4) performing double-layered epitaxial growth: adopting high-purity SiHCl3 deposition, growing a resistivity gradient layer, and then growing a resistivity doped layer. The preparation method adopts a secondary growth process to improve the uniformity of the resistivity of an epitaxial layer; the concentration gradient layer is grown at a low speed, so that formation of misfit dislocation of the epitaxial layer is reduced effectively, the stability and the repeatability of epitaxial electrical properties are improved, and the reliability and the yield of devices are guaranteed.

Description

technical field [0001] The invention relates to the technical field of silicon epitaxial wafers. Background technique [0002] The improvement of the processing capacity of the digital processor has put forward higher requirements for the analog part of the port or analog signal processing. The status of standard MOS in high-speed circuits has been doubted, and various new CMOS process technologies have developed rapidly. Some companies have innovated the original MOS process, among which the use of epitaxial wafers as raw materials to reduce parasitic effects in circuits is one of the most important improvements. Chip speed, integration, power consumption, chip cost, and R&D cycle are important aspects that determine a company's process selection. It is an urgent need to develop qualified epitaxial wafers (mainly P-type materials) for CMOS processes, making standard CMOS processes Development potential in the field of high-speed analog, mixed-signal processing. [0003] C...

AI Technical Summary

Problems solved by technology

In the device manufacturing process, in order to reduce the voltage drop and energy consumption of the substrate part, some P-type epitaxy uses a heavily boron-doped P++ substrate, and the concentration of boron in the substrate is 3×10 19 ~1×10 20 / cm3, while the epitaxial resistivity is only 5-30 ohm cm, the concentration of B atoms drops sharply during epitaxial growth, the atomic lattice changes drastically, and lattice mismatch occurs. Due to the release of mismatch stress, mismatch dislocations are very large. It is easy to form at the interface of P- / P++ silicon epitaxial wafers, and its accompanying penetrating dislocations that penetrate the entire epitaxial layer will increase the leakage current of the device and cause device failure

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